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authorVladimir Zapolskiy <vz@mleia.com>2015-10-01 02:23:36 +0300
committerBrian Norris <computersforpeace@gmail.com>2015-10-04 22:30:49 +0100
commit08d3cd5ef0633df84d119e939d8d1b56c6e4a5e7 (patch)
tree1163d0aeffd29e437d56f1bdbc52b9ccee109d6c
parent641f6342f507cfe671ac5a58768a8473e14ae2ac (diff)
mtd: nand: lpc32xx_slc: fix potential overflow over 4 bits
In case if quotient of controller clock rate to device clock rate does not fit into 4 bit value, choose the maximum acceptable value 0xF, which stands for 16 clocks. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-rw-r--r--drivers/mtd/nand/lpc32xx_slc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c
index 9ac0f3b5554c..a9e8a02cdac5 100644
--- a/drivers/mtd/nand/lpc32xx_slc.c
+++ b/drivers/mtd/nand/lpc32xx_slc.c
@@ -95,7 +95,7 @@
* slc_tac register definitions
**********************************************************************/
/* Computation of clock cycles on basis of controller and device clock rates */
-#define SLCTAC_CLOCKS(c, n, s) (((1 + (c / n)) & 0xF) << s)
+#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, 1 + (c / n), 0xF) << s)
/* Clock setting for RDY write sample wait time in 2*n clocks */
#define SLCTAC_WDR(n) (((n) & 0xF) << 28)