diff options
| author | Gaurav Kohli <gkohli@codeaurora.org> | 2016-11-17 16:36:45 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-12-02 05:26:56 -0800 |
| commit | 0daf7767a625678381bdc95aa5d2fe5db2858aa6 (patch) | |
| tree | 8d4521003e1b29c4fd47d0ec0310713753c1153f | |
| parent | 49093e91832c6edbd13ee1dec25db602c605f5cf (diff) | |
ARM: dts: msm: Enable CX Ipeak Mitigation for MSMFALCON
This enables the assertion of CX ipeak mitigation during
MSS restart.
Change-Id: I113037aabafeacba7079d530ca859833f475f649
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon.dtsi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index ed8bee03b4d0..365b5344f4b9 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -1099,9 +1099,11 @@ <0x1f65000 0x008>, <0x1f64000 0x008>, <0x4180000 0x040>, - <0x00179000 0x004>; + <0x00179000 0x004>, + <0x01fe5048 0x004>; reg-names = "qdsp6_base", "halt_q6", "halt_modem", - "halt_nc", "rmb_base", "restart_reg"; + "halt_nc", "rmb_base", "restart_reg", + "cxip_lm_vote_clear"; clocks = <&clock_rpmcc RPM_XO_CLK_SRC>, <&clock_gcc GCC_MSS_CFG_AHB_CLK>, @@ -1132,6 +1134,7 @@ qcom,qdsp6v62-1-5; memory-region = <&modem_fw_mem>; qcom,mem-protect-id = <0xF>; + qcom,cx-ipeak-vote; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; |