Merge "qpnp-fg-gen3: Add support to configure auto recharge voltage"

3 files changed, 41 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt
index 421379116989..808e18b495d5 100644
--- a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt
+++ b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt
@@ -63,6 +63,14 @@ First Level Node - FG Gen3 device
 	Definition: The voltage threshold (in mV) which upon set will be used
 		    for configuring the low battery voltage threshold.
 
+- qcom,fg-recharge-voltage
+	Usage:      optional
+	Value type: <u32>
+	Definition: The voltage threshold (in mV) based on which the charging
+		    will be resumed once the charging is complete. If this
+		    property is not specified, then the default value will be
+		    4250mV.
+
 - qcom,fg-chg-term-current
 	Usage:      optional
 	Value type: <u32>
diff --git a/drivers/power/qcom-charger/fg-core.h b/drivers/power/qcom-charger/fg-core.h
index d612016b1b79..f0de532f196c 100644
--- a/drivers/power/qcom-charger/fg-core.h
+++ b/drivers/power/qcom-charger/fg-core.h
@@ -151,6 +151,7 @@ enum fg_sram_param_id {
 	FG_SRAM_CHG_TERM_CURR,
 	FG_SRAM_DELTA_SOC_THR,
 	FG_SRAM_RECHARGE_SOC_THR,
+	FG_SRAM_RECHARGE_VBATT_THR,
 	FG_SRAM_KI_COEFF_MED_DISCHG,
 	FG_SRAM_KI_COEFF_HI_DISCHG,
 	FG_SRAM_MAX,
@@ -198,6 +199,7 @@ struct fg_dt_props {
 	int	sys_term_curr_ma;
 	int	delta_soc_thr;
 	int	recharge_soc_thr;
+	int	recharge_volt_thr_mv;
 	int	rsense_sel;
 	int	jeita_thresholds[NUM_JEITA_LEVELS];
 	int	esr_timer_charging;
diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c
index 6ff0e9e45b00..4d2cfc84d455 100644
--- a/drivers/power/qcom-charger/qpnp-fg-gen3.c
+++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c
@@ -112,6 +112,8 @@
 #define EMPTY_VOLT_v2_OFFSET		3
 #define VBATT_LOW_v2_WORD		16
 #define VBATT_LOW_v2_OFFSET		0
+#define RECHARGE_VBATT_THR_v2_WORD	16
+#define RECHARGE_VBATT_THR_v2_OFFSET	1
 #define FLOAT_VOLT_v2_WORD		16
 #define FLOAT_VOLT_v2_OFFSET		2
 
@@ -236,6 +238,9 @@ static struct fg_sram_param pmi8998_v2_sram_params[] = {
 	PARAM(RECHARGE_SOC_THR, RECHARGE_SOC_THR_v2_WORD,
 		RECHARGE_SOC_THR_v2_OFFSET, 1, 256, 100, 0, fg_encode_default,
 		NULL),
+	PARAM(RECHARGE_VBATT_THR, RECHARGE_VBATT_THR_v2_WORD,
+		RECHARGE_VBATT_THR_v2_OFFSET, 1, 1000, 15625, -2000,
+		fg_encode_voltage, NULL),
 	PARAM(ESR_TIMER_DISCHG_MAX, ESR_TIMER_DISCHG_MAX_WORD,
 		ESR_TIMER_DISCHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default,
 		NULL),
@@ -2395,8 +2400,8 @@ static int fg_hw_init(struct fg_chip *chip)
 		return rc;
 	}
 
-	/* This SRAM register is only present in v2.0 */
-	if (chip->pmic_rev_id->rev4 == PMI8998_V2P0_REV4 &&
+	/* This SRAM register is only present in v2.0 and above */
+	if (chip->pmic_rev_id->rev4 >= PMI8998_V2P0_REV4 &&
 		chip->bp.float_volt_uv > 0) {
 		fg_encode(chip->sp, FG_SRAM_FLOAT_VOLT,
 			chip->bp.float_volt_uv / 1000, buf);
@@ -2476,6 +2481,23 @@ static int fg_hw_init(struct fg_chip *chip)
 		}
 	}
 
+	/* This configuration is available only for pmicobalt v2.0 and above */
+	if (chip->pmic_rev_id->rev4 >= PMI8998_V2P0_REV4 &&
+		chip->dt.recharge_volt_thr_mv > 0) {
+		fg_encode(chip->sp, FG_SRAM_RECHARGE_VBATT_THR,
+			chip->dt.recharge_volt_thr_mv, buf);
+		rc = fg_sram_write(chip,
+				chip->sp[FG_SRAM_RECHARGE_VBATT_THR].addr_word,
+				chip->sp[FG_SRAM_RECHARGE_VBATT_THR].addr_byte,
+				buf, chip->sp[FG_SRAM_RECHARGE_VBATT_THR].len,
+				FG_IMA_DEFAULT);
+		if (rc < 0) {
+			pr_err("Error in writing recharge_vbatt_thr, rc=%d\n",
+				rc);
+			return rc;
+		}
+	}
+
 	if (chip->dt.rsense_sel >= SRC_SEL_BATFET &&
 			chip->dt.rsense_sel < SRC_SEL_RESERVED) {
 		rc = fg_masked_write(chip, BATT_INFO_IBATT_SENSING_CFG(chip),
@@ -2935,6 +2957,7 @@ static int fg_parse_ki_coefficients(struct fg_chip *chip)
 
 #define DEFAULT_CUTOFF_VOLT_MV		3200
 #define DEFAULT_EMPTY_VOLT_MV		2800
+#define DEFAULT_RECHARGE_VOLT_MV	4250
 #define DEFAULT_CHG_TERM_CURR_MA	100
 #define DEFAULT_SYS_TERM_CURR_MA	-125
 #define DEFAULT_DELTA_SOC_THR		1
@@ -3096,6 +3119,12 @@ static int fg_parse_dt(struct fg_chip *chip)
 	else
 		chip->dt.recharge_soc_thr = temp;
 
+	rc = of_property_read_u32(node, "qcom,fg-recharge-voltage", &temp);
+	if (rc < 0)
+		chip->dt.recharge_volt_thr_mv = DEFAULT_RECHARGE_VOLT_MV;
+	else
+		chip->dt.recharge_volt_thr_mv = temp;
+
 	rc = of_property_read_u32(node, "qcom,fg-rsense-sel", &temp);
 	if (rc < 0)
 		chip->dt.rsense_sel = SRC_SEL_BATFET_SMB;