Merge "ARM: dts: msm: Update GPUCC clock frequencies for MSMtriton"

4 files changed, 36 insertions, 26 deletions

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
index 9f8ea0d6ef8f..4d8f87225230 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
@@ -4,7 +4,8 @@ Qualcomm Technologies, Inc Graphics Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain only one of the following:
 
-			"qcom,gpucc-msmfalcon"
+			"qcom,gpucc-msmfalcon",
+			"qcom,gpucc-msmtriton"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi
index d96531a5b35a..adef0781de72 100644
--- a/arch/arm/boot/dts/qcom/msmtriton.dtsi
+++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi
@@ -564,7 +564,7 @@
 	};
 
 	clock_gfx: clock-controller@5065000 {
-		compatible = "qcom,gpucc-msmfalcon";
+		compatible = "qcom,gpucc-msmtriton";
 		reg = <0x5065000 0x10000>;
 		vdd_dig_gfx-supply = <&pm2falcon_s3_level>;
 		vdd_mx_gfx-supply = <&pm2falcon_s5_level>;
@@ -572,13 +572,13 @@
 		qcom,gfxfreq-corner =
 			< 0         0>,
 			< 160000000 1>,  /* MinSVS */
-			< 266000000 2>,  /* LowSVS */
+			< 240000000 2>,  /* LowSVS */
 			< 370000000 3>,  /* SVS    */
 			< 465000000 4>,  /* SVS_L1 */
 			< 588000000 5>,  /* NOM    */
 			< 647000000 6>,  /* NOM_L1 */
-			< 700000000 7>,  /* TURBO  */
-			< 750000000 7>;  /* TURBO  */
+			< 700000000 7>,  /* TURBO */
+			< 775000000 7>;  /* TURBO  */
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-msmfalcon.c
index fe7cff443250..9b7dd907a6f3 100644
--- a/drivers/clk/qcom/gpucc-msmfalcon.c
+++ b/drivers/clk/qcom/gpucc-msmfalcon.c
@@ -113,13 +113,7 @@ static struct clk_alpha_pll gpu_pll0_pll_out_main = {
 			.parent_names = (const char *[]){ "xo" },
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_ops,
-			VDD_GPU_PLL_FMAX_MAP6(
-					MIN, 266000000,
-					LOWER, 432000000,
-					LOW, 640000000,
-					LOW_L1, 800000000,
-					NOMINAL, 1020000000,
-					HIGH, 1500000000),
+			VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000),
 		},
 	},
 };
@@ -136,13 +130,7 @@ static struct clk_alpha_pll gpu_pll1_pll_out_main = {
 			.parent_names = (const char *[]){ "xo" },
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_ops,
-			VDD_GPU_PLL_FMAX_MAP6(
-					MIN, 266000000,
-					LOWER, 432000000,
-					LOW, 640000000,
-					LOW_L1, 800000000,
-					NOMINAL, 1020000000,
-					HIGH, 1500000000),
+			VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000),
 		},
 	},
 };
@@ -199,6 +187,19 @@ static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gfx3d_clk_src_triton[] = {
+	F_GFX( 19200000, 0,  1, 0, 0,         0),
+	F_GFX(160000000, 0,  2, 0, 0,  640000000),
+	F_GFX(240000000, 0,  2, 0, 0,  480000000),
+	F_GFX(370000000, 0,  2, 0, 0,  740000000),
+	F_GFX(465000000, 0,  2, 0, 0,  930000000),
+	F_GFX(588000000, 0,  2, 0, 0, 1176000000),
+	F_GFX(647000000, 0,  2, 0, 0, 1294000000),
+	F_GFX(700000000, 0,  2, 0, 0, 1400000000),
+	F_GFX(775000000, 0,  2, 0, 0, 1550000000),
+	{ }
+};
+
 static struct clk_rcg2 gfx3d_clk_src = {
 	.cmd_rcgr = 0x1070,
 	.mnd_width = 0,
@@ -343,6 +344,7 @@ static const struct qcom_cc_desc gpucc_falcon_desc = {
 
 static const struct of_device_id gpucc_falcon_match_table[] = {
 	{ .compatible = "qcom,gpucc-msmfalcon" },
+	{ .compatible = "qcom,gpucc-msmtriton" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, gpucc_falcon_match_table);
@@ -409,6 +411,7 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
+	bool is_triton = 0;
 
 	regmap = qcom_cc_map(pdev, &gpucc_falcon_desc);
 	if (IS_ERR(regmap))
@@ -441,6 +444,17 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 		return PTR_ERR(vdd_gfx.regulator[0]);
 	}
 
+	is_triton = of_device_is_compatible(pdev->dev.of_node,
+					"qcom,gpucc-msmtriton");
+	if (is_triton) {
+		gpu_pll0_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1]
+						= 1550000000;
+		gpu_pll1_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1]
+						= 1550000000;
+		/* Add new frequency table */
+		gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_triton;
+	}
+
 	/* GFX rail fmax data linked to branch clock */
 	of_get_fmax_vdd_class(pdev, &gpucc_gfx3d_clk.clkr.hw,
 						"qcom,gfxfreq-corner", 1);
diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-falcon.h
index 8f9eefe3a89c..75567dbe2329 100644
--- a/drivers/clk/qcom/vdd-level-falcon.h
+++ b/drivers/clk/qcom/vdd-level-falcon.h
@@ -104,15 +104,10 @@
 	},					\
 	.num_rate_max = VDD_DIG_NUM
 
-#define VDD_GPU_PLL_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \
+#define VDD_GPU_PLL_FMAX_MAP1(l1, f1)			 \
 	.vdd_class = &vdd_mx,				\
-	.rate_max = (unsigned long[VDD_DIG_NUM]) {		\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
 		[VDD_DIG_##l1] = (f1),			\
-		[VDD_DIG_##l2] = (f2),			\
-		[VDD_DIG_##l3] = (f3),			\
-		[VDD_DIG_##l4] = (f4),			\
-		[VDD_DIG_##l5] = (f5),			\
-		[VDD_DIG_##l6] = (f6),			\
 	},						\
 	.num_rate_max = VDD_DIG_NUM