summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorLinux Build Service Account <lnxbuild@localhost>2017-03-24 12:12:43 -0700
committerGerrit - the friendly Code Review server <code-review@localhost>2017-03-24 12:12:43 -0700
commit2b2a813f2377263288362bdbaf32e3f5df55968b (patch)
tree99963396135683b096cbc0dec02d27724dae4730
parent3d962a00546bf7084d1892529fe1fbcc5bd248a2 (diff)
parentf38e93e11f0f0daf7116fe0c3ee0da4b4c533824 (diff)
Merge "ARM: dts: msm: Set the rate for camss vfe clock on SDM660 & SDM630"
Diffstat
-rw-r--r--arch/arm/boot/dts/qcom/sdm630-camera.dtsi42
-rw-r--r--arch/arm/boot/dts/qcom/sdm660-camera.dtsi42
2 files changed, 44 insertions, 40 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm630-camera.dtsi b/arch/arm/boot/dts/qcom/sdm630-camera.dtsi
index 82b9b2cf4de8..8b226586ca7b 100644
--- a/arch/arm/boot/dts/qcom/sdm630-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm630-camera.dtsi
@@ -451,11 +451,11 @@
<&clock_mmss MMSS_CAMSS_CSI1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI2_CLK>,
<&clock_mmss MMSS_CAMSS_CSI3_CLK>,
- <&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>,
- <&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"camss_ahb_clk",
@@ -468,10 +468,12 @@
"csi2_pix_clk", "csi3_pix_clk",
"camss_csi0_clk", "camss_csi1_clk",
"camss_csi2_clk", "camss_csi3_clk",
+ "vfe0_clk_src",
"camss_vfe_vfe0_clk",
- "vfe0_clk_src", "camss_csi_vfe0_clk",
+ "camss_csi_vfe0_clk",
+ "vfe1_clk_src",
"camss_vfe_vfe1_clk",
- "vfe1_clk_src", "camss_csi_vfe1_clk";
+ "camss_csi_vfe1_clk";
qcom,clock-rates = <0 0 0 0 0
0 0 0 0
0 0 0 0
@@ -490,10 +492,10 @@
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
- "NO_SET_RATE",
- "INIT_RATE", "NO_SET_RATE",
- "NO_SET_RATE",
- "INIT_RATE", "NO_SET_RATE";
+ "INIT_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "INIT_RATE",
+ "NO_SET_RATE", "NO_SET_RATE";
status = "ok";
};
@@ -516,23 +518,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
- <&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
- "camss_ahb_clk", "camss_top_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
- "camss_vfe_vbif_axi_clk", "vfe_clk_src",
+ "camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
- qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
- 0 0 0 0 0 0 0 0 0 0 0 480000000 0
- 0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
+ qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 480000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
@@ -597,23 +599,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
- <&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
- "camss_ahb_clk", "camss_top_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
- "camss_vfe_vbif_axi_clk", "vfe_clk_src",
+ "camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
- qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
- 0 0 0 0 0 0 0 0 0 0 0 480000000 0
- 0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
+ qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 480000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
diff --git a/arch/arm/boot/dts/qcom/sdm660-camera.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi
index 1f886f7f368f..f3b81b5df1de 100644
--- a/arch/arm/boot/dts/qcom/sdm660-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi
@@ -454,11 +454,11 @@
<&clock_mmss MMSS_CAMSS_CSI1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI2_CLK>,
<&clock_mmss MMSS_CAMSS_CSI3_CLK>,
- <&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>,
- <&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"camss_ahb_clk",
@@ -471,10 +471,12 @@
"csi2_pix_clk", "csi3_pix_clk",
"camss_csi0_clk", "camss_csi1_clk",
"camss_csi2_clk", "camss_csi3_clk",
+ "vfe0_clk_src",
"camss_vfe_vfe0_clk",
- "vfe0_clk_src", "camss_csi_vfe0_clk",
+ "camss_csi_vfe0_clk",
+ "vfe1_clk_src",
"camss_vfe_vfe1_clk",
- "vfe1_clk_src", "camss_csi_vfe1_clk";
+ "camss_csi_vfe1_clk";
qcom,clock-rates = <0 0 0 0 0
0 0 0 0
0 0 0 0
@@ -493,10 +495,10 @@
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
- "NO_SET_RATE",
- "INIT_RATE", "NO_SET_RATE",
- "NO_SET_RATE",
- "INIT_RATE", "NO_SET_RATE";
+ "INIT_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "INIT_RATE",
+ "NO_SET_RATE", "NO_SET_RATE";
status = "ok";
};
@@ -518,23 +520,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
- <&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
- "camss_ahb_clk", "camss_top_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
- "camss_vfe_vbif_axi_clk", "vfe_clk_src",
+ "camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
- qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
- 0 0 0 0 0 0 0 0 0 0 0 480000000 0
- 0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
+ qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 480000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
@@ -599,23 +601,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
- <&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
- "camss_ahb_clk", "camss_top_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
- "camss_vfe_vbif_axi_clk", "vfe_clk_src",
+ "camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
- qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
- 0 0 0 0 0 0 0 0 0 0 0 480000000 0
- 0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
+ qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 480000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-17 18:37:19 +0000