Merge "clk: msm: clock: Update clock frequencies on MSMCOBALT"

6 files changed, 61 insertions, 126 deletions

diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
index 238d68efaba7..de054dc56543 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
@@ -165,21 +165,21 @@
 	compatible = "qcom,gfxcc-cobalt-v2";
 	qcom,gfxfreq-speedbin0 =
 		<         0 0                           0 >,
-		< 189000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >,
-		< 264000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 257000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 342000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >,
-		< 520000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >,
 		< 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >,
 		< 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >,
 		< 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >;
 	qcom,gfxfreq-mx-speedbin0 =
 		<         0                           0 >,
-		< 189000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
-		< 264000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
-		< 520000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
 		< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
 		< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >,
 		< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
diff --git a/arch/arm/boot/dts/qcom/msmhamster.dtsi b/arch/arm/boot/dts/qcom/msmhamster.dtsi
index e87cf7c153ea..4669fa519f5d 100644
--- a/arch/arm/boot/dts/qcom/msmhamster.dtsi
+++ b/arch/arm/boot/dts/qcom/msmhamster.dtsi
@@ -39,24 +39,24 @@
 	compatible = "qcom,gfxcc-hamster";
 	qcom,gfxfreq-speedbin0 =
 		<	  0 0				0 >,
-		< 185000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >,
-		< 285000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 265000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 358000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 434000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 542000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >,
 		< 630000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >,
-		< 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >,
-		< 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+		< 700000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 750000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >;
 	qcom,gfxfreq-mx-speedbin0 =
 		<         0                           0 >,
-		< 185000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
-		< 285000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 265000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 358000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 434000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 		< 542000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
 		< 630000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
-		< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >,
-		< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+		< 700000000 RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 750000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
 };
 
 &tsens0 {
diff --git a/drivers/clk/msm/clock-gpu-cobalt.c b/drivers/clk/msm/clock-gpu-cobalt.c
index 7230c7a2bc04..7cec9be1f42c 100644
--- a/drivers/clk/msm/clock-gpu-cobalt.c
+++ b/drivers/clk/msm/clock-gpu-cobalt.c
@@ -39,8 +39,6 @@ static void __iomem *virt_base_gfx;
 #define gpucc_gpll0_source_val			5
 #define gpu_pll0_pll_out_even_source_val	1
 #define gpu_pll0_pll_out_odd_source_val		2
-#define gpu_pll1_pll_out_even_source_val	3
-#define gpu_pll1_pll_out_odd_source_val		4
 
 #define SW_COLLAPSE_MASK			BIT(0)
 #define GPU_CX_GDSCR_OFFSET			0x1004
@@ -157,65 +155,6 @@ static struct div_clk gpu_pll0_pll_out_odd = {
 	},
 };
 
-static struct alpha_pll_clk gpu_pll1_pll = {
-	.masks = &pll_masks_p,
-	.base = &virt_base_gfx,
-	.offset = GPUCC_GPU_PLL1_PLL_MODE,
-	.enable_config = 0x1,
-	.is_fabia = true,
-	.c = {
-		.rate = 0,
-		.parent = &gpucc_xo.c,
-		.dbg_name = "gpu_pll1_pll",
-		.ops = &clk_ops_fabia_alpha_pll,
-		VDD_GPU_PLL_FMAX_MAP1(MIN, 1300000500),
-		CLK_INIT(gpu_pll1_pll.c),
-	},
-};
-
-static struct div_clk gpu_pll1_pll_out_even = {
-	.base = &virt_base_gfx,
-	.offset = GPUCC_GPU_PLL1_USER_CTL_MODE,
-	.mask = 0xf,
-	.shift = 8,
-	.data = {
-		.max_div = 8,
-		.min_div = 1,
-		.skip_odd_div = true,
-		.allow_div_one = true,
-		.rate_margin = 500,
-	},
-	.ops = &postdiv_reg_ops,
-	.c = {
-		.parent = &gpu_pll1_pll.c,
-		.dbg_name = "gpu_pll1_pll_out_even",
-		.ops = &clk_ops_div,
-		.flags = CLKFLAG_NO_RATE_CACHE,
-		CLK_INIT(gpu_pll1_pll_out_even.c),
-	},
-};
-
-static struct div_clk gpu_pll1_pll_out_odd = {
-	.base = &virt_base_gfx,
-	.offset = GPUCC_GPU_PLL0_USER_CTL_MODE,
-	.mask = 0xf,
-	.shift = 12,
-	.data = {
-		.max_div = 7,
-		.min_div = 3,
-		.skip_even_div = true,
-		.rate_margin = 500,
-	},
-	.ops = &postdiv_reg_ops,
-	.c = {
-		.parent = &gpu_pll1_pll.c,
-		.dbg_name = "gpu_pll1_pll_out_odd",
-		.ops = &clk_ops_div,
-		.flags = CLKFLAG_NO_RATE_CACHE,
-		CLK_INIT(gpu_pll1_pll_out_odd.c),
-	},
-};
-
 static struct clk_freq_tbl ftbl_gfx3d_clk_src[] = {
 	F_SLEW( 171000000,  342000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 251000000,  502000000, gpu_pll0_pll_out_even,    1, 0, 0),
@@ -227,11 +166,11 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src[] = {
 };
 
 static struct clk_freq_tbl ftbl_gfx3d_clk_src_v2[] = {
-	F_SLEW( 189000000,  378000000, gpu_pll0_pll_out_even,    1, 0, 0),
-	F_SLEW( 264000000,  528000000, gpu_pll0_pll_out_even,    1, 0, 0),
+	F_SLEW( 180000000,  360000000, gpu_pll0_pll_out_even,    1, 0, 0),
+	F_SLEW( 257000000,  514000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 342000000,  684000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 414000000,  828000000, gpu_pll0_pll_out_even,    1, 0, 0),
-	F_SLEW( 520000000, 1040000000, gpu_pll0_pll_out_even,    1, 0, 0),
+	F_SLEW( 515000000, 1030000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 596000000, 1192000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 670000000, 1340000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 710000000, 1420000000, gpu_pll0_pll_out_even,    1, 0, 0),
@@ -239,14 +178,14 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src_v2[] = {
 };
 
 static struct clk_freq_tbl ftbl_gfx3d_clk_src_vq[] = {
-	F_SLEW( 185000000,  370000000, gpu_pll0_pll_out_even,    1, 0, 0),
-	F_SLEW( 285000000,  570000000, gpu_pll0_pll_out_even,    1, 0, 0),
+	F_SLEW( 180000000,  360000000, gpu_pll0_pll_out_even,    1, 0, 0),
+	F_SLEW( 265000000,  530000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 358000000,  716000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 434000000,  868000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 542000000, 1084000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_SLEW( 630000000, 1260000000, gpu_pll0_pll_out_even,    1, 0, 0),
-	F_SLEW( 670000000, 1340000000, gpu_pll1_pll_out_even,    1, 0, 0),
-	F_SLEW( 710000000, 1420000000, gpu_pll1_pll_out_even,    1, 0, 0),
+	F_SLEW( 700000000, 1400000000, gpu_pll0_pll_out_even,    1, 0, 0),
+	F_SLEW( 750000000, 1500000000, gpu_pll0_pll_out_even,    1, 0, 0),
 	F_END
 };
 
@@ -659,9 +598,6 @@ static struct clk_lookup msm_clocks_gfxcc_cobalt[] = {
 	CLK_LIST(gpu_pll0_pll),
 	CLK_LIST(gpu_pll0_pll_out_even),
 	CLK_LIST(gpu_pll0_pll_out_odd),
-	CLK_LIST(gpu_pll1_pll),
-	CLK_LIST(gpu_pll1_pll_out_even),
-	CLK_LIST(gpu_pll1_pll_out_odd),
 	CLK_LIST(gfx3d_clk_src),
 	CLK_LIST(gpucc_gfx3d_clk),
 	CLK_LIST(gpucc_mx_clk),
@@ -671,14 +607,12 @@ static struct clk_lookup msm_clocks_gfxcc_cobalt[] = {
 static void msm_gfxcc_hamster_fixup(void)
 {
 	gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
-	gpu_pll1_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
 	gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_vq;
 }
 
 static void msm_gfxcc_cobalt_v2_fixup(void)
 {
 	gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
-	gpu_pll1_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
 	gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2;
 }
 
diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-cobalt.c
index 288abb133743..2da10a2e4780 100644
--- a/drivers/clk/msm/clock-mmss-cobalt.c
+++ b/drivers/clk/msm/clock-mmss-cobalt.c
@@ -274,7 +274,7 @@ static struct rcg_clk csi0_clk_src = {
 	.c = {
 		.dbg_name = "csi0_clk_src",
 		.ops = &clk_ops_rcg,
-		VDD_DIG_FMAX_MAP4(LOWER, 164570000, LOW, 256000000,
+		VDD_DIG_FMAX_MAP4(LOWER, 164571429, LOW, 256000000,
 					NOMINAL, 384000000, HIGH, 576000000),
 		CLK_INIT(csi0_clk_src.c),
 	},
@@ -292,6 +292,9 @@ static struct clk_freq_tbl ftbl_vfe_clk_src[] = {
 
 static struct clk_freq_tbl ftbl_vfe_clk_src_vq[] = {
 	F_MM( 200000000,    mmsscc_gpll0,    3,    0,     0),
+	F_MM( 300000000,    mmsscc_gpll0,    2,    0,     0),
+	F_MM( 320000000,  mmpll7_pll_out,    3,    0,     0),
+	F_MM( 384000000,  mmpll4_pll_out,    2,    0,     0),
 	F_MM( 404000000,  mmpll0_pll_out,    2,    0,     0),
 	F_MM( 480000000,  mmpll7_pll_out,    2,    0,     0),
 	F_MM( 576000000, mmpll10_pll_out,    1,    0,     0),
@@ -367,16 +370,6 @@ static struct clk_freq_tbl ftbl_maxi_clk_src[] = {
 	F_END
 };
 
-static struct clk_freq_tbl ftbl_maxi_clk_src_vq[] = {
-	F_MM(  19200000,        mmsscc_xo,    1,    0,     0),
-	F_MM(  75000000, mmsscc_gpll0_div,    4,    0,     0),
-	F_MM( 171428571,     mmsscc_gpll0,  3.5,    0,     0),
-	F_MM( 240000000,     mmsscc_gpll0,  2.5,    0,     0),
-	F_MM( 323200000,   mmpll0_pll_out,  2.5,    0,     0),
-	F_MM( 406000000,   mmpll1_pll_out,    2,    0,     0),
-	F_END
-};
-
 static struct rcg_clk maxi_clk_src = {
 	.cmd_rcgr_reg = MMSS_MAXI_CMD_RCGR,
 	.set_rate = set_rate_hid,
@@ -592,18 +585,11 @@ static struct clk_freq_tbl ftbl_fd_core_clk_src[] = {
 	F_END
 };
 
-static struct clk_freq_tbl ftbl_fd_core_clk_src_v2[] = {
-	F_MM( 100000000,    mmsscc_gpll0,    6,    0,     0),
-	F_MM( 404000000,  mmpll0_pll_out,    2,    0,     0),
-	F_MM( 480000000,  mmpll7_pll_out,    2,    0,     0),
-	F_MM( 576000000, mmpll10_pll_out,    1,    0,     0),
-	F_END
-};
-
 static struct clk_freq_tbl ftbl_fd_core_clk_src_vq[] = {
 	F_MM( 100000000,    mmsscc_gpll0,    6,    0,     0),
 	F_MM( 200000000,    mmsscc_gpll0,    3,    0,     0),
-	F_MM( 400000000,    mmsscc_gpll0,  1.5,    0,     0),
+	F_MM( 404000000,  mmpll0_pll_out,    2,    0,     0),
+	F_MM( 480000000,  mmpll7_pll_out,    2,    0,     0),
 	F_MM( 576000000, mmpll10_pll_out,    1,    0,     0),
 	F_END
 };
@@ -2677,60 +2663,81 @@ static void msm_mmsscc_hamster_fixup(void)
 	vfe1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000;
 
 	csi0_clk_src.freq_tbl = ftbl_csi_clk_src_vq;
-	csi0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csi0_clk_src.c.fmax[VDD_DIG_LOW] = 274290000;
+	csi0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000;
 	csi1_clk_src.freq_tbl = ftbl_csi_clk_src_vq;
-	csi1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csi1_clk_src.c.fmax[VDD_DIG_LOW] = 274290000;
+	csi1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000;
 	csi2_clk_src.freq_tbl = ftbl_csi_clk_src_vq;
-	csi2_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csi2_clk_src.c.fmax[VDD_DIG_LOW] = 274290000;
+	csi2_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000;
 	csi3_clk_src.freq_tbl = ftbl_csi_clk_src_vq;
-	csi3_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csi3_clk_src.c.fmax[VDD_DIG_LOW] = 274290000;
+	csi3_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000;
 
 	cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_vq;
-	cpp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000;
+	cpp_clk_src.c.fmax[VDD_DIG_LOW] = 384000000;
+	cpp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000;
 	jpeg0_clk_src.freq_tbl = ftbl_jpeg0_clk_src_vq;
 	jpeg0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000;
 	csiphy_clk_src.freq_tbl = ftbl_csiphy_clk_src_vq;
+	csiphy_clk_src.c.fmax[VDD_DIG_LOW] = 274290000;
 	csiphy_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
 	fd_core_clk_src.freq_tbl = ftbl_fd_core_clk_src_vq;
-	fd_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 400000000;
+	fd_core_clk_src.c.fmax[VDD_DIG_LOW] = 404000000;
+	fd_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000;
 
 	csi0phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333;
 	csi1phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333;
 	csi2phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333;
 
 	mdp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 330000000;
+	dp_pixel_clk_src.c.fmax[VDD_DIG_LOWER] = 154000000;
 	extpclk_clk_src.c.fmax[VDD_DIG_LOW] = 312500000;
 	extpclk_clk_src.c.fmax[VDD_DIG_LOW_L1] = 375000000;
 	rot_clk_src.c.fmax[VDD_DIG_LOW_L1] = 330000000;
 
-	maxi_clk_src.freq_tbl = ftbl_maxi_clk_src_vq;
 	video_core_clk_src.freq_tbl = ftbl_video_core_clk_src_vq;
 	video_core_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000;
 	video_core_clk_src.c.fmax[VDD_DIG_LOW] = 269330000;
-	video_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000;
+	video_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;
 	video_core_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000;
 	video_core_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000;
 
 	video_subcore0_clk_src.freq_tbl = ftbl_video_subcore_clk_src_vq;
 	video_subcore0_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000;
 	video_subcore0_clk_src.c.fmax[VDD_DIG_LOW] = 269330000;
-	video_subcore0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000;
+	video_subcore0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;
 	video_subcore0_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000;
 	video_subcore0_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000;
 
 	video_subcore1_clk_src.freq_tbl = ftbl_video_subcore_clk_src_vq;
 	video_subcore1_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000;
 	video_subcore1_clk_src.c.fmax[VDD_DIG_LOW] = 269330000;
-	video_subcore1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000;
+	video_subcore1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;
 	video_subcore1_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000;
 	video_subcore1_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000;
 };
 
 static void msm_mmsscc_v2_fixup(void)
 {
-	fd_core_clk_src.freq_tbl = ftbl_fd_core_clk_src_v2;
-	fd_core_clk_src.c.fmax[VDD_DIG_LOW] = 404000000;
-	fd_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000;
+	cpp_clk_src.c.fmax[VDD_DIG_LOW] = 200000000;
+	cpp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000;
+	csi0_clk_src.c.fmax[VDD_DIG_LOW] = 256000000;
+	csi0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csi1_clk_src.c.fmax[VDD_DIG_LOW] = 256000000;
+	csi1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csi2_clk_src.c.fmax[VDD_DIG_LOW] = 256000000;
+	csi2_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csi3_clk_src.c.fmax[VDD_DIG_LOW] = 256000000;
+	csi3_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000;
+	csiphy_clk_src.c.fmax[VDD_DIG_LOW] = 256000000;
+
+	dp_pixel_clk_src.c.fmax[VDD_DIG_LOWER] = 148380000;
+
+	video_subcore0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;
+	video_subcore1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;
+	video_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;
 }
 
 int msm_mmsscc_cobalt_probe(struct platform_device *pdev)
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h
index 28efd55ea8f6..85e28a9edc03 100644
--- a/include/dt-bindings/clock/msm-clocks-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-cobalt.h
@@ -484,10 +484,6 @@
 #define clk_gpu_pll0_pll_out_even		0xb0ed5009
 #define clk_gpu_pll0_pll_out_odd		0x08c5a8a5
 #define clk_gpu_pll0_postdiv_clk		0x76c19f3c
-#define clk_gpu_pll1_pll			0x09ac81ef
-#define clk_gpu_pll1_pll_out_even		0xa503de04
-#define clk_gpu_pll1_pll_out_odd		0x1c205dfb
-#define clk_gpu_pll1_postdiv_clk		0xdf546700
 #define clk_gpucc_mx_clk			0x1edbb879
 #define clk_gpucc_gcc_dbg_clk			0x9ae8cd3c
 #define clk_gfxcc_dbg_clk			0x3ed47625
diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
index 7ef57256d8f0..6f0e35511cc9 100644
--- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
@@ -235,8 +235,6 @@
 
 #define GPUCC_GPU_PLL0_PLL_MODE					0x00000
 #define GPUCC_GPU_PLL0_USER_CTL_MODE				0x0000C
-#define GPUCC_GPU_PLL1_PLL_MODE					0x00040
-#define GPUCC_GPU_PLL1_USER_CTL_MODE				0x0004C
 #define GPUCC_GFX3D_CMD_RCGR					0x01070
 #define GPUCC_RBBMTIMER_CMD_RCGR				0x010B0
 #define GPUCC_GFX3D_ISENSE_CMD_RCGR				0x01100