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authorzhaoyuan <yzhao@codeaurora.org>2017-01-13 19:52:00 +0800
committerzhaoyuan <yzhao@codeaurora.org>2017-01-17 12:24:32 +0800
commit42017fe489621ac6021019bd49923fcba504503c (patch)
tree7284502f68f688a5408999d3a145fcee51d40cf3
parent1e19092380d35d94eace0c081443317311bfe5d2 (diff)
ARM: dts: msm: Add QTC800H device node to SDM660 QRD SKUs
Add QTC800H device node (hbtp_input) for SDM660 QRD. Add AVDD and VDDIO power rail for power on/off sync. Also add reset pin configuration. Change-Id: I0fb11c27ffae7a9eae55f8f9dc76d71929e68afa Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
-rw-r--r--arch/arm/boot/dts/qcom/sdm660-qrd.dtsi50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi
index 8f60b9a77808..b16b994de725 100644
--- a/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi
@@ -120,6 +120,38 @@
};
};
+&tlmm {
+ pmx_ts_rst_active {
+ ts_rst_active: ts_rst_active {
+ mux {
+ pins = "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_rst_suspend {
+ ts_rst_suspend: ts_rst_suspend {
+ mux {
+ pins = "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+};
+
&soc {
gpio_keys {
compatible = "gpio-keys";
@@ -135,6 +167,24 @@
debounce-interval = <15>;
};
};
+
+ hbtp {
+ compatible = "qcom,hbtp-input";
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_rst_active>;
+ pinctrl-1 = <&ts_rst_suspend>;
+ vcc_ana-supply = <&pm660l_l3>;
+ vcc_dig-supply = <&pm660_l13>;
+ qcom,afe-load = <20000>;
+ qcom,afe-vtg-min = <3008000>;
+ qcom,afe-vtg-max = <3008000>;
+ qcom,dig-load = <40000>;
+ qcom,dig-vtg-min = <1808000>;
+ qcom,dig-vtg-max = <1808000>;
+ qcom,fb-resume-delay-us = <10000>;
+ qcom,afe-power-on-delay-us = <1000>;
+ qcom,afe-power-off-delay-us = <6>;
+ };
};
/ {