diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-05-09 15:38:55 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-15 22:41:11 -0700 |
| commit | 4622a2f4260b7d6a523909a4d86fa66000f36324 (patch) | |
| tree | b1268647a7fe8d8cccc29f86cde4b867cb3d31d5 | |
| parent | dc2b0c10a106b71c995617c0c78fc216585a4390 (diff) | |
clk: msm: clock-gcc-cobalt: Update the pcie_aux_clk_src frequency
The pcie_aux_clk_src needs to run at XO frequency instead
of at 1MHz. Update the clock driver to support that.
CRs-Fixed: 1013278
Change-Id: Id8a92b0f36f71ed50726504d1e5b3feab4cfa512
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
| -rw-r--r-- | drivers/clk/msm/clock-gcc-cobalt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index 6f40e36ef5d9..3e2eb0dbc2bf 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -242,7 +242,7 @@ static struct rcg_clk usb30_master_clk_src = { }; static struct clk_freq_tbl ftbl_pcie_aux_clk_src[] = { - F( 1010526, cxo_clk_src, 1, 1, 19), + F( 19200000, cxo_clk_src, 1, 0, 0), F_END }; |