diff options
| author | Jordan Crouse <jcrouse@codeaurora.org> | 2016-02-01 08:22:10 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:19:21 -0700 |
| commit | 47c274395a89348c4e17b1f8a0f05c82c3bc85a3 (patch) | |
| tree | 7d56ba42da4887ba8e4db045c3420a92e2bc9e08 | |
| parent | a139a9b6056416085f11600e0296622eeb419309 (diff) | |
msm: kgsl: Correct protected mode range for 5XX UCHE registers
The start offset for protected mode ranges needs to be aligned with
the block size. 0xE87 is not aligned with 16 (1 << 4). The hardware
assumes alignment internally so it turns out that 0xE80 - 0xE8F is
the range that gets protected. Luckily for us that this is the range
we want protected so nothing critical has been left unprotected, but
the software should reflect the hardware to prevent incorrect
assumptions.
CRs-Fixed: 968713
Change-Id: Ic0dedbad6ec7be5cc473afbbc52655663ea65159
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| -rw-r--r-- | drivers/gpu/msm/adreno_a5xx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c index 33aaec92aec1..763e08ac1067 100644 --- a/drivers/gpu/msm/adreno_a5xx.c +++ b/drivers/gpu/msm/adreno_a5xx.c @@ -483,7 +483,7 @@ static void a5xx_protect_init(struct adreno_device *adreno_dev) adreno_set_protected_registers(adreno_dev, &index, 0xE70, 4); /* UCHE registers */ - adreno_set_protected_registers(adreno_dev, &index, 0xE87, 4); + adreno_set_protected_registers(adreno_dev, &index, 0xE80, ilog2(16)); /* SMMU registers */ iommu_regs = kgsl_mmu_get_prot_regs(&device->mmu); |