diff options
| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2013-09-16 10:37:01 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-09-26 15:13:50 -0400 |
| commit | 551ed409690d05a3af7a330b188501fd1593e6af (patch) | |
| tree | ebc9dc55568ab0ceef24fac2b1dc279ce8d25a34 | |
| parent | c6cc47b101c547c328cae06c2d8813a8e69549bf (diff) | |
ath9k: Remove incorrect diversity initialization
Fast antenna diversity is required only for single chain
chips and the diversity initialization is done in the
per-family board setup routines. Enabling of diversity
should be done based on the calibrated EEPROM/OTP data,
doing it for all chips is incorrect.
Remove the code that sets the fast_div bit for all cards, since
the documentation for the AR_PHY_CCK_DETECT register says:
reg 642: sig_detect_cck
enable_ant_fast_div : Only used for single chain chips.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar5008_phy.c | 3 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.c | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c index 9e4e2a693774..cb6435e7c6f5 100644 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c @@ -631,9 +631,6 @@ static void ar5008_hw_override_ini(struct ath_hw *ah, REG_WRITE(ah, AR_PCU_MISC_MODE2, val); } - REG_SET_BIT(ah, AR_PHY_CCK_DETECT, - AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); - if (AR_SREV_9280_20_OR_LATER(ah)) return; /* diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index ec37213fb765..0131ba2f5d51 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c @@ -632,9 +632,6 @@ static void ar9003_hw_override_ini(struct ath_hw *ah) AR_PCU_MISC_MODE2_CFP_IGNORE; REG_WRITE(ah, AR_PCU_MISC_MODE2, val); - REG_SET_BIT(ah, AR_PHY_CCK_DETECT, - AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); - if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, AR_GLB_SWREG_DISCONT_EN_BT_WLAN); |