diff options
| author | Casey Piper <cpiper@codeaurora.org> | 2015-03-11 18:25:03 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:43 -0700 |
| commit | 5a356b88c83549424c97d1a011d255ae685e9b7c (patch) | |
| tree | fb8597bcfdaf57e5275abb8857d79eaf41484bb6 | |
| parent | 0b02573adc815a45607d263693a9ed02148801f9 (diff) | |
clk: mdss: write lane mode when powering on HDMI PHY
To improve the timing margin, lane mode selection
needs to be written during the HDMI PHY startup
sequence. This prevents a timing failure when
VDDCX or VCCA_CORE are applied rather than the
nominal value.
Change-Id: I2ed54f63903a473eca12fb4d8f3b542585397dae
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c b/drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c index 0d60ed8654a6..8bcd795f9633 100644 --- a/drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c +++ b/drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c @@ -762,6 +762,10 @@ static int hdmi_thulium_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk) QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_LANE_MODE, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_LANE_MODE, 0x03); MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, QSERDES_TX_L0_TX_BAND, cfg.tx_l0_tx_band); |