Merge "pinctrl: qcom: Update TLMM configuration for msmfalcon"

1 files changed, 500 insertions, 430 deletions

diff --git a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c b/drivers/pinctrl/qcom/pinctrl-msmfalcon.c
index 254b2a1dd765..45db409eb7c1 100644
--- a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c
+++ b/drivers/pinctrl/qcom/pinctrl-msmfalcon.c
@@ -25,9 +25,9 @@
 		.ngroups = ARRAY_SIZE(fname##_groups),	\
 	}
 
-#define SOUTH	0x00500000
-#define WEST	0x00100000
-#define EAST	0x00900000
+#define NORTH	0x00900000
+#define CENTER	0x00500000
+#define SOUTH	0x00100000
 #define REG_SIZE 0x1000
 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
 	{					        \
@@ -204,13 +204,16 @@ static const struct pinctrl_pin_desc msmfalcon_pins[] = {
 	PINCTRL_PIN(108, "GPIO_108"),
 	PINCTRL_PIN(109, "GPIO_109"),
 	PINCTRL_PIN(110, "GPIO_110"),
-	PINCTRL_PIN(111, "SDC1_CLK"),
-	PINCTRL_PIN(112, "SDC1_CMD"),
-	PINCTRL_PIN(113, "SDC1_DATA"),
-	PINCTRL_PIN(114, "SDC2_CLK"),
-	PINCTRL_PIN(115, "SDC2_CMD"),
-	PINCTRL_PIN(116, "SDC2_DATA"),
-	PINCTRL_PIN(117, "SDC1_RCLK"),
+	PINCTRL_PIN(111, "GPIO_111"),
+	PINCTRL_PIN(112, "GPIO_112"),
+	PINCTRL_PIN(113, "GPIO_113"),
+	PINCTRL_PIN(114, "SDC1_CLK"),
+	PINCTRL_PIN(115, "SDC1_CMD"),
+	PINCTRL_PIN(116, "SDC1_DATA"),
+	PINCTRL_PIN(117, "SDC2_CLK"),
+	PINCTRL_PIN(118, "SDC2_CMD"),
+	PINCTRL_PIN(119, "SDC2_DATA"),
+	PINCTRL_PIN(120, "SDC1_RCLK"),
 };
 
 #define DECLARE_MSM_GPIO_PINS(pin) \
@@ -326,92 +329,101 @@ DECLARE_MSM_GPIO_PINS(107);
 DECLARE_MSM_GPIO_PINS(108);
 DECLARE_MSM_GPIO_PINS(109);
 DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
 
-static const unsigned int sdc1_clk_pins[] = { 111 };
-static const unsigned int sdc1_cmd_pins[] = { 112 };
-static const unsigned int sdc1_data_pins[] = { 113 };
-static const unsigned int sdc2_clk_pins[] = { 114 };
-static const unsigned int sdc2_cmd_pins[] = { 115 };
-static const unsigned int sdc2_data_pins[] = { 116 };
-static const unsigned int sdc1_rclk_pins[] = { 117 };
+static const unsigned int sdc1_clk_pins[] = { 114 };
+static const unsigned int sdc1_cmd_pins[] = { 115 };
+static const unsigned int sdc1_data_pins[] = { 116 };
+static const unsigned int sdc2_clk_pins[] = { 117 };
+static const unsigned int sdc2_cmd_pins[] = { 118 };
+static const unsigned int sdc2_data_pins[] = { 119 };
+static const unsigned int sdc1_rclk_pins[] = { 120 };
 
 enum msmfalcon_functions {
 	msm_mux_blsp_spi1,
 	msm_mux_gpio,
+	msm_mux_blsp_uim1,
 	msm_mux_tgu_ch0,
-	msm_mux_tgu_ch1,
+	msm_mux_qdss_gpio4,
+	msm_mux_atest_gpsadc1,
 	msm_mux_blsp_uart1,
+	msm_mux_SMB_STAT,
+	msm_mux_phase_flag14,
+	msm_mux_blsp_i2c2,
+	msm_mux_phase_flag31,
 	msm_mux_blsp_spi3,
 	msm_mux_wlan1_adc1,
 	msm_mux_atest_usb13,
-	msm_mux_bimc_dte1,
-	msm_mux_wlan1_adc0,
-	msm_mux_atest_usb12,
-	msm_mux_bimc_dte0,
+	msm_mux_tgu_ch1,
+	msm_mux_qdss_gpio5,
+	msm_mux_atest_gpsadc0,
 	msm_mux_blsp_i2c1,
-	msm_mux_blsp_uim1,
 	msm_mux_ddr_bist,
 	msm_mux_atest_tsens2,
 	msm_mux_atest_usb1,
 	msm_mux_blsp_spi2,
-	msm_mux_phase_flag3,
-	msm_mux_phase_flag14,
-	msm_mux_blsp_i2c2,
 	msm_mux_blsp_uim2,
-	msm_mux_phase_flag31,
+	msm_mux_phase_flag3,
+	msm_mux_bimc_dte1,
+	msm_mux_wlan1_adc0,
+	msm_mux_atest_usb12,
+	msm_mux_bimc_dte0,
 	msm_mux_blsp_i2c3,
-	msm_mux_atest_gpsadc1,
 	msm_mux_wlan2_adc1,
 	msm_mux_atest_usb11,
 	msm_mux_dbg_out,
-	msm_mux_atest_gpsadc0,
 	msm_mux_wlan2_adc0,
 	msm_mux_atest_usb10,
+	msm_mux_RCM_MARKER,
 	msm_mux_blsp_spi4,
 	msm_mux_pri_mi2s,
 	msm_mux_phase_flag26,
-	msm_mux_qdss_gpio4,
+	msm_mux_qdss_cti,
+	msm_mux_DP_HOT,
 	msm_mux_pri_mi2s_ws,
 	msm_mux_phase_flag27,
-	msm_mux_qdss_gpio5,
 	msm_mux_blsp_i2c4,
 	msm_mux_phase_flag28,
 	msm_mux_blsp_uart5,
 	msm_mux_blsp_spi5,
+	msm_mux_blsp_uim5,
 	msm_mux_phase_flag5,
 	msm_mux_blsp_i2c5,
-	msm_mux_blsp_uim5,
 	msm_mux_blsp_spi6,
 	msm_mux_blsp_uart2,
-	msm_mux_qdss_cti,
-	msm_mux_sec_mi2s,
-	msm_mux_sndwire_clk,
-	msm_mux_phase_flag17,
-	msm_mux_vsense_clkout,
-	msm_mux_sndwire_data,
-	msm_mux_phase_flag18,
-	msm_mux_blsp_i2c7,
-	msm_mux_wsa_en1,
-	msm_mux_phase_flag19,
+	msm_mux_blsp_uim6,
 	msm_mux_phase_flag11,
 	msm_mux_vsense_data0,
 	msm_mux_blsp_i2c6,
-	msm_mux_blsp_uim6,
 	msm_mux_phase_flag12,
 	msm_mux_vsense_data1,
 	msm_mux_phase_flag13,
 	msm_mux_vsense_mode,
 	msm_mux_blsp_spi7,
 	msm_mux_BLSP_UART,
+	msm_mux_sec_mi2s,
+	msm_mux_sndwire_clk,
+	msm_mux_phase_flag17,
+	msm_mux_vsense_clkout,
+	msm_mux_sndwire_data,
+	msm_mux_phase_flag18,
+	msm_mux_WSA_SPKR,
+	msm_mux_blsp_i2c7,
+	msm_mux_phase_flag19,
 	msm_mux_vfr_1,
-	msm_mux_wsa_en2,
 	msm_mux_phase_flag20,
+	msm_mux_NFC_INT,
 	msm_mux_blsp_spi,
 	msm_mux_m_voc,
 	msm_mux_phase_flag21,
+	msm_mux_NFC_EN,
 	msm_mux_phase_flag22,
+	msm_mux_NFC_DWL,
 	msm_mux_BLSP_I2C,
 	msm_mux_phase_flag23,
+	msm_mux_NFC_ESE,
 	msm_mux_pwr_modem,
 	msm_mux_phase_flag24,
 	msm_mux_qdss_gpio,
@@ -427,88 +439,92 @@ enum msmfalcon_functions {
 	msm_mux_qspi_data2,
 	msm_mux_jitter_bist,
 	msm_mux_qdss_gpio3,
+	msm_mux_qdss_gpio7,
+	msm_mux_FL_R3LED,
+	msm_mux_CCI_TIMER0,
+	msm_mux_FL_STROBE,
+	msm_mux_CCI_TIMER1,
+	msm_mux_CAM_LDO1,
+	msm_mux_mdss_vsync0,
+	msm_mux_mdss_vsync1,
+	msm_mux_mdss_vsync2,
+	msm_mux_mdss_vsync3,
+	msm_mux_qdss_gpio9,
+	msm_mux_CAM_IRQ,
+	msm_mux_atest_usb2,
 	msm_mux_cci_i2c,
 	msm_mux_pll_bypassnl,
 	msm_mux_atest_tsens,
+	msm_mux_atest_usb21,
 	msm_mux_pll_reset,
-	msm_mux_qdss_gpio9,
-	msm_mux_CAM_IRQ,
+	msm_mux_atest_usb23,
+	msm_mux_qdss_gpio6,
 	msm_mux_CCI_TIMER3,
 	msm_mux_CCI_ASYNC,
 	msm_mux_qspi_cs,
 	msm_mux_qdss_gpio10,
-	msm_mux_CAM4_STANDBY,
+	msm_mux_CAM3_STANDBY,
 	msm_mux_CCI_TIMER4,
 	msm_mux_qdss_gpio11,
-	msm_mux_bt_reset,
+	msm_mux_CAM_LDO2,
 	msm_mux_cci_async,
 	msm_mux_qdss_gpio12,
-	msm_mux_CAM1_RST,
-	msm_mux_qdss_gpio6,
-	msm_mux_qdss_gpio7,
-	msm_mux_FL_FRONT,
-	msm_mux_CCI_TIMER0,
-	msm_mux_qdss_gpio8,
-	msm_mux_FL_STROBE,
-	msm_mux_CCI_TIMER1,
-	msm_mux_LASER_CE,
-	msm_mux_mdss_vsync0,
-	msm_mux_mdss_vsync1,
-	msm_mux_mdss_vsync2,
-	msm_mux_mdss_vsync3,
+	msm_mux_CAM0_RST,
 	msm_mux_qdss_gpio13,
-	msm_mux_CAM2_RST,
+	msm_mux_CAM1_RST,
 	msm_mux_qspi_clk,
 	msm_mux_phase_flag30,
 	msm_mux_qdss_gpio14,
-	msm_mux_CAM3_RST,
 	msm_mux_qspi_resetn,
 	msm_mux_phase_flag1,
 	msm_mux_qdss_gpio15,
-	msm_mux_CAM1_STANDBY,
+	msm_mux_CAM0_STANDBY,
 	msm_mux_phase_flag2,
-	msm_mux_CAM2_STANDBY,
+	msm_mux_CAM1_STANDBY,
 	msm_mux_phase_flag9,
-	msm_mux_CAM3_STANDBY,
+	msm_mux_CAM2_STANDBY,
 	msm_mux_qspi_data3,
 	msm_mux_phase_flag15,
-	msm_mux_CAM4_RST,
+	msm_mux_qdss_gpio8,
+	msm_mux_CAM3_RST,
 	msm_mux_CCI_TIMER2,
 	msm_mux_phase_flag16,
+	msm_mux_LCD0_RESET,
 	msm_mux_phase_flag6,
-	msm_mux_RCM_MARKER2,
+	msm_mux_SD_CARD,
 	msm_mux_phase_flag29,
-	msm_mux_SS_SWITCH,
+	msm_mux_DP_EN,
 	msm_mux_phase_flag25,
+	msm_mux_USBC_ORIENTATION,
 	msm_mux_phase_flag10,
+	msm_mux_atest_usb20,
 	msm_mux_gcc_gp1,
 	msm_mux_phase_flag4,
-	msm_mux_USB_DIR,
+	msm_mux_atest_usb22,
 	msm_mux_USB_PHY,
 	msm_mux_gcc_gp2,
 	msm_mux_atest_char,
 	msm_mux_mdp_vsync,
 	msm_mux_gcc_gp3,
 	msm_mux_atest_char3,
-	msm_mux_Lcd_mode,
-	msm_mux_EDP_HOT,
+	msm_mux_FORCE_TOUCH,
 	msm_mux_cri_trng0,
 	msm_mux_atest_char2,
 	msm_mux_cri_trng1,
 	msm_mux_atest_char1,
+	msm_mux_AUDIO_USBC,
 	msm_mux_audio_ref,
 	msm_mux_MDP_VSYNC,
 	msm_mux_cri_trng,
 	msm_mux_atest_char0,
 	msm_mux_US_EURO,
-	msm_mux_KEY_FOCUS,
-	msm_mux_NAV_PPS,
+	msm_mux_LCD_BACKLIGHT,
 	msm_mux_blsp_spi8,
 	msm_mux_sp_cmu,
-	msm_mux_SLT_PWR,
+	msm_mux_NAV_PPS,
+	msm_mux_GPS_TX,
 	msm_mux_adsp_ext,
 	msm_mux_TS_RESET,
-	msm_mux_TS_INT,
 	msm_mux_ssc_irq,
 	msm_mux_isense_dbg,
 	msm_mux_phase_flag0,
@@ -516,8 +532,10 @@ enum msmfalcon_functions {
 	msm_mux_phase_flag8,
 	msm_mux_tsense_pwm1,
 	msm_mux_tsense_pwm2,
+	msm_mux_SENSOR_RST,
+	msm_mux_WMSS_RESETN,
 	msm_mux_HAPTICS_PWM,
-	msm_mux_wmss_reset,
+	msm_mux_GPS_eLNA,
 	msm_mux_mss_lte,
 	msm_mux_uim2_data,
 	msm_mux_uim2_clk,
@@ -529,12 +547,12 @@ enum msmfalcon_functions {
 	msm_mux_uim1_present,
 	msm_mux_uim_batt,
 	msm_mux_pa_indicator,
-	msm_mux_ssbi_gnss,
 	msm_mux_ldo_en,
 	msm_mux_ldo_update,
 	msm_mux_qlink_request,
 	msm_mux_qlink_enable,
 	msm_mux_prng_rosc,
+	msm_mux_LCD_PWR,
 	msm_mux_NA,
 };
 
@@ -542,27 +560,44 @@ static const char * const blsp_spi1_groups[] = {
 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio46",
 };
 static const char * const gpio_groups[] = {
-	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
-	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
-	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
-	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
-	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
-	"gpio36", "gpio37", "gpio38", "gpio39", "gpio53", "gpio57", "gpio59",
-	"gpio61", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
-	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
-	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
-	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
-	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio6", "gpio7", "gpio8",
+	"gpio9", "gpio10", "gpio11", "gpio14", "gpio15", "gpio16", "gpio17",
+	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24",
+	"gpio25", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37",
+	"gpio38", "gpio39", "gpio57", "gpio58", "gpio59", "gpio61", "gpio65",
+	"gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio86", "gpio87",
+	"gpio88", "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
+	"gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
+	"gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
+	"gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
+};
+static const char * const blsp_uim1_groups[] = {
+	"gpio0", "gpio1",
 };
 static const char * const tgu_ch0_groups[] = {
 	"gpio0",
 };
-static const char * const tgu_ch1_groups[] = {
-	"gpio1",
+static const char * const qdss_gpio4_groups[] = {
+	"gpio0", "gpio36",
+};
+static const char * const atest_gpsadc1_groups[] = {
+	"gpio0",
 };
 static const char * const blsp_uart1_groups[] = {
 	"gpio0", "gpio1", "gpio2", "gpio3",
 };
+static const char * const SMB_STAT_groups[] = {
+	"gpio5",
+};
+static const char * const phase_flag14_groups[] = {
+	"gpio5",
+};
+static const char * const blsp_i2c2_groups[] = {
+	"gpio6", "gpio7",
+};
+static const char * const phase_flag31_groups[] = {
+	"gpio6",
+};
 static const char * const blsp_spi3_groups[] = {
 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio30", "gpio65",
 };
@@ -572,24 +607,18 @@ static const char * const wlan1_adc1_groups[] = {
 static const char * const atest_usb13_groups[] = {
 	"gpio8",
 };
-static const char * const bimc_dte1_groups[] = {
-	"gpio8", "gpio10",
-};
-static const char * const wlan1_adc0_groups[] = {
-	"gpio9",
+static const char * const tgu_ch1_groups[] = {
+	"gpio1",
 };
-static const char * const atest_usb12_groups[] = {
-	"gpio9",
+static const char * const qdss_gpio5_groups[] = {
+	"gpio1", "gpio37",
 };
-static const char * const bimc_dte0_groups[] = {
-	"gpio9", "gpio11",
+static const char * const atest_gpsadc0_groups[] = {
+	"gpio1",
 };
 static const char * const blsp_i2c1_groups[] = {
 	"gpio2", "gpio3",
 };
-static const char * const blsp_uim1_groups[] = {
-	"gpio2", "gpio3",
-};
 static const char * const ddr_bist_groups[] = {
 	"gpio3", "gpio8", "gpio9", "gpio10",
 };
@@ -602,27 +631,27 @@ static const char * const atest_usb1_groups[] = {
 static const char * const blsp_spi2_groups[] = {
 	"gpio4", "gpio5", "gpio6", "gpio7",
 };
+static const char * const blsp_uim2_groups[] = {
+	"gpio4", "gpio5",
+};
 static const char * const phase_flag3_groups[] = {
 	"gpio4",
 };
-static const char * const phase_flag14_groups[] = {
-	"gpio5",
+static const char * const bimc_dte1_groups[] = {
+	"gpio8", "gpio10",
 };
-static const char * const blsp_i2c2_groups[] = {
-	"gpio6", "gpio7",
+static const char * const wlan1_adc0_groups[] = {
+	"gpio9",
 };
-static const char * const blsp_uim2_groups[] = {
-	"gpio6", "gpio7",
+static const char * const atest_usb12_groups[] = {
+	"gpio9",
 };
-static const char * const phase_flag31_groups[] = {
-	"gpio6",
+static const char * const bimc_dte0_groups[] = {
+	"gpio9", "gpio11",
 };
 static const char * const blsp_i2c3_groups[] = {
 	"gpio10", "gpio11",
 };
-static const char * const atest_gpsadc1_groups[] = {
-	"gpio10",
-};
 static const char * const wlan2_adc1_groups[] = {
 	"gpio10",
 };
@@ -632,15 +661,15 @@ static const char * const atest_usb11_groups[] = {
 static const char * const dbg_out_groups[] = {
 	"gpio11",
 };
-static const char * const atest_gpsadc0_groups[] = {
-	"gpio11",
-};
 static const char * const wlan2_adc0_groups[] = {
 	"gpio11",
 };
 static const char * const atest_usb10_groups[] = {
 	"gpio11",
 };
+static const char * const RCM_MARKER_groups[] = {
+	"gpio12", "gpio13",
+};
 static const char * const blsp_spi4_groups[] = {
 	"gpio12", "gpio13", "gpio14", "gpio15",
 };
@@ -650,8 +679,12 @@ static const char * const pri_mi2s_groups[] = {
 static const char * const phase_flag26_groups[] = {
 	"gpio12",
 };
-static const char * const qdss_gpio4_groups[] = {
-	"gpio12", "gpio36",
+static const char * const qdss_cti_groups[] = {
+	"gpio12", "gpio13", "gpio21", "gpio49", "gpio50", "gpio53", "gpio55",
+	"gpio66",
+};
+static const char * const DP_HOT_groups[] = {
+	"gpio13",
 };
 static const char * const pri_mi2s_ws_groups[] = {
 	"gpio13",
@@ -659,9 +692,6 @@ static const char * const pri_mi2s_ws_groups[] = {
 static const char * const phase_flag27_groups[] = {
 	"gpio13",
 };
-static const char * const qdss_gpio5_groups[] = {
-	"gpio13", "gpio37",
-};
 static const char * const blsp_i2c4_groups[] = {
 	"gpio14", "gpio15",
 };
@@ -674,51 +704,23 @@ static const char * const blsp_uart5_groups[] = {
 static const char * const blsp_spi5_groups[] = {
 	"gpio16", "gpio17", "gpio18", "gpio19",
 };
+static const char * const blsp_uim5_groups[] = {
+	"gpio16", "gpio17",
+};
 static const char * const phase_flag5_groups[] = {
 	"gpio17",
 };
 static const char * const blsp_i2c5_groups[] = {
 	"gpio18", "gpio19",
 };
-static const char * const blsp_uim5_groups[] = {
-	"gpio18", "gpio19",
-};
 static const char * const blsp_spi6_groups[] = {
 	"gpio20", "gpio21", "gpio22", "gpio23",
 };
 static const char * const blsp_uart2_groups[] = {
 	"gpio20", "gpio21", "gpio22", "gpio23",
 };
-static const char * const qdss_cti_groups[] = {
-	"gpio20", "gpio21", "gpio24", "gpio25", "gpio26", "gpio49", "gpio50",
-	"gpio61",
-};
-static const char * const sec_mi2s_groups[] = {
-	"gpio24", "gpio25", "gpio26", "gpio27", "gpio62",
-};
-static const char * const sndwire_clk_groups[] = {
-	"gpio24",
-};
-static const char * const phase_flag17_groups[] = {
-	"gpio24",
-};
-static const char * const vsense_clkout_groups[] = {
-	"gpio24",
-};
-static const char * const sndwire_data_groups[] = {
-	"gpio25",
-};
-static const char * const phase_flag18_groups[] = {
-	"gpio25",
-};
-static const char * const blsp_i2c7_groups[] = {
-	"gpio26", "gpio27",
-};
-static const char * const wsa_en1_groups[] = {
-	"gpio26",
-};
-static const char * const phase_flag19_groups[] = {
-	"gpio26",
+static const char * const blsp_uim6_groups[] = {
+	"gpio20", "gpio21",
 };
 static const char * const phase_flag11_groups[] = {
 	"gpio21",
@@ -729,9 +731,6 @@ static const char * const vsense_data0_groups[] = {
 static const char * const blsp_i2c6_groups[] = {
 	"gpio22", "gpio23",
 };
-static const char * const blsp_uim6_groups[] = {
-	"gpio22", "gpio23",
-};
 static const char * const phase_flag12_groups[] = {
 	"gpio22",
 };
@@ -751,15 +750,42 @@ static const char * const BLSP_UART_groups[] = {
 	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30",
 	"gpio31",
 };
-static const char * const vfr_1_groups[] = {
-	"gpio27",
+static const char * const sec_mi2s_groups[] = {
+	"gpio24", "gpio25", "gpio26", "gpio27", "gpio62",
+};
+static const char * const sndwire_clk_groups[] = {
+	"gpio24",
+};
+static const char * const phase_flag17_groups[] = {
+	"gpio24",
+};
+static const char * const vsense_clkout_groups[] = {
+	"gpio24",
+};
+static const char * const sndwire_data_groups[] = {
+	"gpio25",
+};
+static const char * const phase_flag18_groups[] = {
+	"gpio25",
+};
+static const char * const WSA_SPKR_groups[] = {
+	"gpio26", "gpio27",
 };
-static const char * const wsa_en2_groups[] = {
+static const char * const blsp_i2c7_groups[] = {
+	"gpio26", "gpio27",
+};
+static const char * const phase_flag19_groups[] = {
+	"gpio26",
+};
+static const char * const vfr_1_groups[] = {
 	"gpio27",
 };
 static const char * const phase_flag20_groups[] = {
 	"gpio27",
 };
+static const char * const NFC_INT_groups[] = {
+	"gpio28",
+};
 static const char * const blsp_spi_groups[] = {
 	"gpio28", "gpio29", "gpio30", "gpio31", "gpio40", "gpio41", "gpio44",
 	"gpio52",
@@ -770,15 +796,24 @@ static const char * const m_voc_groups[] = {
 static const char * const phase_flag21_groups[] = {
 	"gpio28",
 };
+static const char * const NFC_EN_groups[] = {
+	"gpio29",
+};
 static const char * const phase_flag22_groups[] = {
 	"gpio29",
 };
+static const char * const NFC_DWL_groups[] = {
+	"gpio30",
+};
 static const char * const BLSP_I2C_groups[] = {
 	"gpio30", "gpio31", "gpio44", "gpio52",
 };
 static const char * const phase_flag23_groups[] = {
 	"gpio30",
 };
+static const char * const NFC_ESE_groups[] = {
+	"gpio31",
+};
 static const char * const pwr_modem_groups[] = {
 	"gpio31",
 };
@@ -786,7 +821,7 @@ static const char * const phase_flag24_groups[] = {
 	"gpio31",
 };
 static const char * const qdss_gpio_groups[] = {
-	"gpio31", "gpio41", "gpio68", "gpio69",
+	"gpio31", "gpio52", "gpio68", "gpio69",
 };
 static const char * const cam_mclk_groups[] = {
 	"gpio32", "gpio33", "gpio34", "gpio35",
@@ -795,7 +830,7 @@ static const char * const pwr_nav_groups[] = {
 	"gpio32",
 };
 static const char * const qdss_gpio0_groups[] = {
-	"gpio32", "gpio62",
+	"gpio32", "gpio67",
 };
 static const char * const qspi_data0_groups[] = {
 	"gpio33",
@@ -822,7 +857,46 @@ static const char * const jitter_bist_groups[] = {
 	"gpio35",
 };
 static const char * const qdss_gpio3_groups[] = {
-	"gpio35", "gpio65",
+	"gpio35", "gpio56",
+};
+static const char * const qdss_gpio7_groups[] = {
+	"gpio39", "gpio71",
+};
+static const char * const FL_R3LED_groups[] = {
+	"gpio40",
+};
+static const char * const CCI_TIMER0_groups[] = {
+	"gpio40",
+};
+static const char * const FL_STROBE_groups[] = {
+	"gpio41",
+};
+static const char * const CCI_TIMER1_groups[] = {
+	"gpio41",
+};
+static const char * const CAM_LDO1_groups[] = {
+	"gpio42",
+};
+static const char * const mdss_vsync0_groups[] = {
+	"gpio42",
+};
+static const char * const mdss_vsync1_groups[] = {
+	"gpio42",
+};
+static const char * const mdss_vsync2_groups[] = {
+	"gpio42",
+};
+static const char * const mdss_vsync3_groups[] = {
+	"gpio42",
+};
+static const char * const qdss_gpio9_groups[] = {
+	"gpio42", "gpio76",
+};
+static const char * const CAM_IRQ_groups[] = {
+	"gpio43",
+};
+static const char * const atest_usb2_groups[] = {
+	"gpio35",
 };
 static const char * const cci_i2c_groups[] = {
 	"gpio36", "gpio37", "gpio38", "gpio39",
@@ -833,14 +907,17 @@ static const char * const pll_bypassnl_groups[] = {
 static const char * const atest_tsens_groups[] = {
 	"gpio36",
 };
+static const char * const atest_usb21_groups[] = {
+	"gpio36",
+};
 static const char * const pll_reset_groups[] = {
 	"gpio37",
 };
-static const char * const qdss_gpio9_groups[] = {
-	"gpio42", "gpio76",
+static const char * const atest_usb23_groups[] = {
+	"gpio37",
 };
-static const char * const CAM_IRQ_groups[] = {
-	"gpio43",
+static const char * const qdss_gpio6_groups[] = {
+	"gpio38", "gpio70",
 };
 static const char * const CCI_TIMER3_groups[] = {
 	"gpio43",
@@ -854,7 +931,7 @@ static const char * const qspi_cs_groups[] = {
 static const char * const qdss_gpio10_groups[] = {
 	"gpio43", "gpio77",
 };
-static const char * const CAM4_STANDBY_groups[] = {
+static const char * const CAM3_STANDBY_groups[] = {
 	"gpio44",
 };
 static const char * const CCI_TIMER4_groups[] = {
@@ -863,7 +940,7 @@ static const char * const CCI_TIMER4_groups[] = {
 static const char * const qdss_gpio11_groups[] = {
 	"gpio44", "gpio79",
 };
-static const char * const bt_reset_groups[] = {
+static const char * const CAM_LDO2_groups[] = {
 	"gpio45",
 };
 static const char * const cci_async_groups[] = {
@@ -872,49 +949,13 @@ static const char * const cci_async_groups[] = {
 static const char * const qdss_gpio12_groups[] = {
 	"gpio45", "gpio80",
 };
-static const char * const CAM1_RST_groups[] = {
+static const char * const CAM0_RST_groups[] = {
 	"gpio46",
 };
-static const char * const qdss_gpio6_groups[] = {
-	"gpio38", "gpio70",
-};
-static const char * const qdss_gpio7_groups[] = {
-	"gpio39", "gpio71",
-};
-static const char * const FL_FRONT_groups[] = {
-	"gpio40",
-};
-static const char * const CCI_TIMER0_groups[] = {
-	"gpio40",
-};
-static const char * const qdss_gpio8_groups[] = {
-	"gpio40", "gpio75",
-};
-static const char * const FL_STROBE_groups[] = {
-	"gpio41",
-};
-static const char * const CCI_TIMER1_groups[] = {
-	"gpio41",
-};
-static const char * const LASER_CE_groups[] = {
-	"gpio42",
-};
-static const char * const mdss_vsync0_groups[] = {
-	"gpio42",
-};
-static const char * const mdss_vsync1_groups[] = {
-	"gpio42",
-};
-static const char * const mdss_vsync2_groups[] = {
-	"gpio42",
-};
-static const char * const mdss_vsync3_groups[] = {
-	"gpio42",
-};
 static const char * const qdss_gpio13_groups[] = {
 	"gpio46", "gpio78",
 };
-static const char * const CAM2_RST_groups[] = {
+static const char * const CAM1_RST_groups[] = {
 	"gpio47",
 };
 static const char * const qspi_clk_groups[] = {
@@ -926,9 +967,6 @@ static const char * const phase_flag30_groups[] = {
 static const char * const qdss_gpio14_groups[] = {
 	"gpio47", "gpio72",
 };
-static const char * const CAM3_RST_groups[] = {
-	"gpio48",
-};
 static const char * const qspi_resetn_groups[] = {
 	"gpio48",
 };
@@ -938,19 +976,19 @@ static const char * const phase_flag1_groups[] = {
 static const char * const qdss_gpio15_groups[] = {
 	"gpio48", "gpio73",
 };
-static const char * const CAM1_STANDBY_groups[] = {
+static const char * const CAM0_STANDBY_groups[] = {
 	"gpio49",
 };
 static const char * const phase_flag2_groups[] = {
 	"gpio49",
 };
-static const char * const CAM2_STANDBY_groups[] = {
+static const char * const CAM1_STANDBY_groups[] = {
 	"gpio50",
 };
 static const char * const phase_flag9_groups[] = {
 	"gpio50",
 };
-static const char * const CAM3_STANDBY_groups[] = {
+static const char * const CAM2_STANDBY_groups[] = {
 	"gpio51",
 };
 static const char * const qspi_data3_groups[] = {
@@ -959,7 +997,10 @@ static const char * const qspi_data3_groups[] = {
 static const char * const phase_flag15_groups[] = {
 	"gpio51",
 };
-static const char * const CAM4_RST_groups[] = {
+static const char * const qdss_gpio8_groups[] = {
+	"gpio51", "gpio75",
+};
+static const char * const CAM3_RST_groups[] = {
 	"gpio52",
 };
 static const char * const CCI_TIMER2_groups[] = {
@@ -968,32 +1009,41 @@ static const char * const CCI_TIMER2_groups[] = {
 static const char * const phase_flag16_groups[] = {
 	"gpio52",
 };
+static const char * const LCD0_RESET_groups[] = {
+	"gpio53",
+};
 static const char * const phase_flag6_groups[] = {
 	"gpio53",
 };
-static const char * const RCM_MARKER2_groups[] = {
+static const char * const SD_CARD_groups[] = {
 	"gpio54",
 };
 static const char * const phase_flag29_groups[] = {
 	"gpio54",
 };
-static const char * const SS_SWITCH_groups[] = {
-	"gpio55", "gpio56",
+static const char * const DP_EN_groups[] = {
+	"gpio55",
 };
 static const char * const phase_flag25_groups[] = {
 	"gpio55",
 };
+static const char * const USBC_ORIENTATION_groups[] = {
+	"gpio56",
+};
 static const char * const phase_flag10_groups[] = {
 	"gpio56",
 };
+static const char * const atest_usb20_groups[] = {
+	"gpio56",
+};
 static const char * const gcc_gp1_groups[] = {
 	"gpio57", "gpio78",
 };
 static const char * const phase_flag4_groups[] = {
 	"gpio57",
 };
-static const char * const USB_DIR_groups[] = {
-	"gpio58",
+static const char * const atest_usb22_groups[] = {
+	"gpio57",
 };
 static const char * const USB_PHY_groups[] = {
 	"gpio58",
@@ -1013,11 +1063,8 @@ static const char * const gcc_gp3_groups[] = {
 static const char * const atest_char3_groups[] = {
 	"gpio59",
 };
-static const char * const Lcd_mode_groups[] = {
-	"gpio60",
-};
-static const char * const EDP_HOT_groups[] = {
-	"gpio60",
+static const char * const FORCE_TOUCH_groups[] = {
+	"gpio60", "gpio73",
 };
 static const char * const cri_trng0_groups[] = {
 	"gpio60",
@@ -1031,6 +1078,9 @@ static const char * const cri_trng1_groups[] = {
 static const char * const atest_char1_groups[] = {
 	"gpio61",
 };
+static const char * const AUDIO_USBC_groups[] = {
+	"gpio62",
+};
 static const char * const audio_ref_groups[] = {
 	"gpio62",
 };
@@ -1046,20 +1096,20 @@ static const char * const atest_char0_groups[] = {
 static const char * const US_EURO_groups[] = {
 	"gpio63",
 };
-static const char * const KEY_FOCUS_groups[] = {
+static const char * const LCD_BACKLIGHT_groups[] = {
 	"gpio64",
 };
-static const char * const NAV_PPS_groups[] = {
-	"gpio64", "gpio65", "gpio98", "gpio98",
-};
 static const char * const blsp_spi8_groups[] = {
 	"gpio64", "gpio76",
 };
 static const char * const sp_cmu_groups[] = {
 	"gpio64",
 };
-static const char * const SLT_PWR_groups[] = {
-	"gpio65",
+static const char * const NAV_PPS_groups[] = {
+	"gpio65", "gpio65", "gpio80", "gpio80", "gpio98", "gpio98",
+};
+static const char * const GPS_TX_groups[] = {
+	"gpio65", "gpio80", "gpio98",
 };
 static const char * const adsp_ext_groups[] = {
 	"gpio65",
@@ -1067,12 +1117,9 @@ static const char * const adsp_ext_groups[] = {
 static const char * const TS_RESET_groups[] = {
 	"gpio66",
 };
-static const char * const TS_INT_groups[] = {
-	"gpio67",
-};
 static const char * const ssc_irq_groups[] = {
-	"gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74",
-	"gpio75", "gpio76", "gpio77",
+	"gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio74",
+	"gpio75", "gpio76",
 };
 static const char * const isense_dbg_groups[] = {
 	"gpio68",
@@ -1092,12 +1139,18 @@ static const char * const tsense_pwm1_groups[] = {
 static const char * const tsense_pwm2_groups[] = {
 	"gpio71",
 };
-static const char * const HAPTICS_PWM_groups[] = {
+static const char * const SENSOR_RST_groups[] = {
+	"gpio77",
+};
+static const char * const WMSS_RESETN_groups[] = {
 	"gpio78",
 };
-static const char * const wmss_reset_groups[] = {
+static const char * const HAPTICS_PWM_groups[] = {
 	"gpio79",
 };
+static const char * const GPS_eLNA_groups[] = {
+	"gpio80",
+};
 static const char * const mss_lte_groups[] = {
 	"gpio81", "gpio82",
 };
@@ -1131,9 +1184,6 @@ static const char * const uim_batt_groups[] = {
 static const char * const pa_indicator_groups[] = {
 	"gpio92",
 };
-static const char * const ssbi_gnss_groups[] = {
-	"gpio94",
-};
 static const char * const ldo_en_groups[] = {
 	"gpio97",
 };
@@ -1149,84 +1199,93 @@ static const char * const qlink_enable_groups[] = {
 static const char * const prng_rosc_groups[] = {
 	"gpio102",
 };
+static const char * const LCD_PWR_groups[] = {
+	"gpio113",
+};
 
 static const struct msm_function msmfalcon_functions[] = {
 	FUNCTION(blsp_spi1),
 	FUNCTION(gpio),
+	FUNCTION(blsp_uim1),
 	FUNCTION(tgu_ch0),
-	FUNCTION(tgu_ch1),
+	FUNCTION(qdss_gpio4),
+	FUNCTION(atest_gpsadc1),
 	FUNCTION(blsp_uart1),
+	FUNCTION(SMB_STAT),
+	FUNCTION(phase_flag14),
+	FUNCTION(blsp_i2c2),
+	FUNCTION(phase_flag31),
 	FUNCTION(blsp_spi3),
 	FUNCTION(wlan1_adc1),
 	FUNCTION(atest_usb13),
-	FUNCTION(bimc_dte1),
-	FUNCTION(wlan1_adc0),
-	FUNCTION(atest_usb12),
-	FUNCTION(bimc_dte0),
+	FUNCTION(tgu_ch1),
+	FUNCTION(qdss_gpio5),
+	FUNCTION(atest_gpsadc0),
 	FUNCTION(blsp_i2c1),
-	FUNCTION(blsp_uim1),
 	FUNCTION(ddr_bist),
 	FUNCTION(atest_tsens2),
 	FUNCTION(atest_usb1),
 	FUNCTION(blsp_spi2),
-	FUNCTION(phase_flag3),
-	FUNCTION(phase_flag14),
-	FUNCTION(blsp_i2c2),
 	FUNCTION(blsp_uim2),
-	FUNCTION(phase_flag31),
+	FUNCTION(phase_flag3),
+	FUNCTION(bimc_dte1),
+	FUNCTION(wlan1_adc0),
+	FUNCTION(atest_usb12),
+	FUNCTION(bimc_dte0),
 	FUNCTION(blsp_i2c3),
-	FUNCTION(atest_gpsadc1),
 	FUNCTION(wlan2_adc1),
 	FUNCTION(atest_usb11),
 	FUNCTION(dbg_out),
-	FUNCTION(atest_gpsadc0),
 	FUNCTION(wlan2_adc0),
 	FUNCTION(atest_usb10),
+	FUNCTION(RCM_MARKER),
 	FUNCTION(blsp_spi4),
 	FUNCTION(pri_mi2s),
 	FUNCTION(phase_flag26),
-	FUNCTION(qdss_gpio4),
+	FUNCTION(qdss_cti),
+	FUNCTION(DP_HOT),
 	FUNCTION(pri_mi2s_ws),
 	FUNCTION(phase_flag27),
-	FUNCTION(qdss_gpio5),
 	FUNCTION(blsp_i2c4),
 	FUNCTION(phase_flag28),
 	FUNCTION(blsp_uart5),
 	FUNCTION(blsp_spi5),
+	FUNCTION(blsp_uim5),
 	FUNCTION(phase_flag5),
 	FUNCTION(blsp_i2c5),
-	FUNCTION(blsp_uim5),
 	FUNCTION(blsp_spi6),
 	FUNCTION(blsp_uart2),
-	FUNCTION(qdss_cti),
-	FUNCTION(sec_mi2s),
-	FUNCTION(sndwire_clk),
-	FUNCTION(phase_flag17),
-	FUNCTION(vsense_clkout),
-	FUNCTION(sndwire_data),
-	FUNCTION(phase_flag18),
-	FUNCTION(blsp_i2c7),
-	FUNCTION(wsa_en1),
-	FUNCTION(phase_flag19),
+	FUNCTION(blsp_uim6),
 	FUNCTION(phase_flag11),
 	FUNCTION(vsense_data0),
 	FUNCTION(blsp_i2c6),
-	FUNCTION(blsp_uim6),
 	FUNCTION(phase_flag12),
 	FUNCTION(vsense_data1),
 	FUNCTION(phase_flag13),
 	FUNCTION(vsense_mode),
 	FUNCTION(blsp_spi7),
 	FUNCTION(BLSP_UART),
+	FUNCTION(sec_mi2s),
+	FUNCTION(sndwire_clk),
+	FUNCTION(phase_flag17),
+	FUNCTION(vsense_clkout),
+	FUNCTION(sndwire_data),
+	FUNCTION(phase_flag18),
+	FUNCTION(WSA_SPKR),
+	FUNCTION(blsp_i2c7),
+	FUNCTION(phase_flag19),
 	FUNCTION(vfr_1),
-	FUNCTION(wsa_en2),
 	FUNCTION(phase_flag20),
+	FUNCTION(NFC_INT),
 	FUNCTION(blsp_spi),
 	FUNCTION(m_voc),
 	FUNCTION(phase_flag21),
+	FUNCTION(NFC_EN),
 	FUNCTION(phase_flag22),
+	FUNCTION(NFC_DWL),
 	FUNCTION(BLSP_I2C),
 	FUNCTION(phase_flag23),
+	FUNCTION(NFC_ESE),
 	FUNCTION(pwr_modem),
 	FUNCTION(phase_flag24),
 	FUNCTION(qdss_gpio),
@@ -1242,88 +1301,92 @@ static const struct msm_function msmfalcon_functions[] = {
 	FUNCTION(qspi_data2),
 	FUNCTION(jitter_bist),
 	FUNCTION(qdss_gpio3),
+	FUNCTION(qdss_gpio7),
+	FUNCTION(FL_R3LED),
+	FUNCTION(CCI_TIMER0),
+	FUNCTION(FL_STROBE),
+	FUNCTION(CCI_TIMER1),
+	FUNCTION(CAM_LDO1),
+	FUNCTION(mdss_vsync0),
+	FUNCTION(mdss_vsync1),
+	FUNCTION(mdss_vsync2),
+	FUNCTION(mdss_vsync3),
+	FUNCTION(qdss_gpio9),
+	FUNCTION(CAM_IRQ),
+	FUNCTION(atest_usb2),
 	FUNCTION(cci_i2c),
 	FUNCTION(pll_bypassnl),
 	FUNCTION(atest_tsens),
+	FUNCTION(atest_usb21),
 	FUNCTION(pll_reset),
-	FUNCTION(qdss_gpio9),
-	FUNCTION(CAM_IRQ),
+	FUNCTION(atest_usb23),
+	FUNCTION(qdss_gpio6),
 	FUNCTION(CCI_TIMER3),
 	FUNCTION(CCI_ASYNC),
 	FUNCTION(qspi_cs),
 	FUNCTION(qdss_gpio10),
-	FUNCTION(CAM4_STANDBY),
+	FUNCTION(CAM3_STANDBY),
 	FUNCTION(CCI_TIMER4),
 	FUNCTION(qdss_gpio11),
-	FUNCTION(bt_reset),
+	FUNCTION(CAM_LDO2),
 	FUNCTION(cci_async),
 	FUNCTION(qdss_gpio12),
-	FUNCTION(CAM1_RST),
-	FUNCTION(qdss_gpio6),
-	FUNCTION(qdss_gpio7),
-	FUNCTION(FL_FRONT),
-	FUNCTION(CCI_TIMER0),
-	FUNCTION(qdss_gpio8),
-	FUNCTION(FL_STROBE),
-	FUNCTION(CCI_TIMER1),
-	FUNCTION(LASER_CE),
-	FUNCTION(mdss_vsync0),
-	FUNCTION(mdss_vsync1),
-	FUNCTION(mdss_vsync2),
-	FUNCTION(mdss_vsync3),
+	FUNCTION(CAM0_RST),
 	FUNCTION(qdss_gpio13),
-	FUNCTION(CAM2_RST),
+	FUNCTION(CAM1_RST),
 	FUNCTION(qspi_clk),
 	FUNCTION(phase_flag30),
 	FUNCTION(qdss_gpio14),
-	FUNCTION(CAM3_RST),
 	FUNCTION(qspi_resetn),
 	FUNCTION(phase_flag1),
 	FUNCTION(qdss_gpio15),
-	FUNCTION(CAM1_STANDBY),
+	FUNCTION(CAM0_STANDBY),
 	FUNCTION(phase_flag2),
-	FUNCTION(CAM2_STANDBY),
+	FUNCTION(CAM1_STANDBY),
 	FUNCTION(phase_flag9),
-	FUNCTION(CAM3_STANDBY),
+	FUNCTION(CAM2_STANDBY),
 	FUNCTION(qspi_data3),
 	FUNCTION(phase_flag15),
-	FUNCTION(CAM4_RST),
+	FUNCTION(qdss_gpio8),
+	FUNCTION(CAM3_RST),
 	FUNCTION(CCI_TIMER2),
 	FUNCTION(phase_flag16),
+	FUNCTION(LCD0_RESET),
 	FUNCTION(phase_flag6),
-	FUNCTION(RCM_MARKER2),
+	FUNCTION(SD_CARD),
 	FUNCTION(phase_flag29),
-	FUNCTION(SS_SWITCH),
+	FUNCTION(DP_EN),
 	FUNCTION(phase_flag25),
+	FUNCTION(USBC_ORIENTATION),
 	FUNCTION(phase_flag10),
+	FUNCTION(atest_usb20),
 	FUNCTION(gcc_gp1),
 	FUNCTION(phase_flag4),
-	FUNCTION(USB_DIR),
+	FUNCTION(atest_usb22),
 	FUNCTION(USB_PHY),
 	FUNCTION(gcc_gp2),
 	FUNCTION(atest_char),
 	FUNCTION(mdp_vsync),
 	FUNCTION(gcc_gp3),
 	FUNCTION(atest_char3),
-	FUNCTION(Lcd_mode),
-	FUNCTION(EDP_HOT),
+	FUNCTION(FORCE_TOUCH),
 	FUNCTION(cri_trng0),
 	FUNCTION(atest_char2),
 	FUNCTION(cri_trng1),
 	FUNCTION(atest_char1),
+	FUNCTION(AUDIO_USBC),
 	FUNCTION(audio_ref),
 	FUNCTION(MDP_VSYNC),
 	FUNCTION(cri_trng),
 	FUNCTION(atest_char0),
 	FUNCTION(US_EURO),
-	FUNCTION(KEY_FOCUS),
-	FUNCTION(NAV_PPS),
+	FUNCTION(LCD_BACKLIGHT),
 	FUNCTION(blsp_spi8),
 	FUNCTION(sp_cmu),
-	FUNCTION(SLT_PWR),
+	FUNCTION(NAV_PPS),
+	FUNCTION(GPS_TX),
 	FUNCTION(adsp_ext),
 	FUNCTION(TS_RESET),
-	FUNCTION(TS_INT),
 	FUNCTION(ssc_irq),
 	FUNCTION(isense_dbg),
 	FUNCTION(phase_flag0),
@@ -1331,8 +1394,10 @@ static const struct msm_function msmfalcon_functions[] = {
 	FUNCTION(phase_flag8),
 	FUNCTION(tsense_pwm1),
 	FUNCTION(tsense_pwm2),
+	FUNCTION(SENSOR_RST),
+	FUNCTION(WMSS_RESETN),
 	FUNCTION(HAPTICS_PWM),
-	FUNCTION(wmss_reset),
+	FUNCTION(GPS_eLNA),
 	FUNCTION(mss_lte),
 	FUNCTION(uim2_data),
 	FUNCTION(uim2_clk),
@@ -1344,153 +1409,155 @@ static const struct msm_function msmfalcon_functions[] = {
 	FUNCTION(uim1_present),
 	FUNCTION(uim_batt),
 	FUNCTION(pa_indicator),
-	FUNCTION(ssbi_gnss),
 	FUNCTION(ldo_en),
 	FUNCTION(ldo_update),
 	FUNCTION(qlink_request),
 	FUNCTION(qlink_enable),
 	FUNCTION(prng_rosc),
+	FUNCTION(LCD_PWR),
 };
 
 static const struct msm_pingroup msmfalcon_groups[] = {
-	PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, tgu_ch0, NA, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, tgu_ch1, NA, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, blsp_uim1, NA, NA,
-		 NA, NA, NA),
-	PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, blsp_uim1,
-		 ddr_bist, NA, atest_tsens2, atest_usb1, NA),
-	PINGROUP(4, WEST, blsp_spi2, phase_flag3, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(5, WEST, blsp_spi2, phase_flag14, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(6, WEST, blsp_spi2, blsp_i2c2, blsp_uim2, phase_flag31, NA,
-		 NA, NA, NA, NA),
-	PINGROUP(7, WEST, blsp_spi2, blsp_i2c2, blsp_uim2, NA, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(8, WEST, blsp_spi3, ddr_bist, NA, NA, wlan1_adc1, atest_usb13,
-		 bimc_dte1, NA, NA),
-	PINGROUP(9, WEST, blsp_spi3, ddr_bist, NA, NA, wlan1_adc0, atest_usb12,
-		 bimc_dte0, NA, NA),
-	PINGROUP(10, WEST, blsp_spi3, blsp_i2c3, ddr_bist, NA, atest_gpsadc1,
-		 wlan2_adc1, atest_usb11, bimc_dte1, NA),
-	PINGROUP(11, WEST, blsp_spi3, blsp_i2c3, dbg_out, atest_gpsadc0,
-		 wlan2_adc0, atest_usb10, bimc_dte0, NA, NA),
-	PINGROUP(12, SOUTH, blsp_spi4, pri_mi2s, phase_flag26, qdss_gpio4, NA,
+	PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA,
+		 qdss_gpio4, atest_gpsadc1, NA),
+	PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA,
+		 qdss_gpio5, atest_gpsadc0, NA),
+	PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, NA, NA,
+		 atest_tsens2, atest_usb1, NA),
+	PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, NA, phase_flag3, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, NA, phase_flag14, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, NA, phase_flag31, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(8, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc1,
+		 atest_usb13, bimc_dte1, NA),
+	PINGROUP(9, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc0,
+		 atest_usb12, bimc_dte0, NA),
+	PINGROUP(10, NORTH, blsp_spi3, blsp_i2c3, ddr_bist, NA, NA, wlan2_adc1,
+		 atest_usb11, bimc_dte1, NA),
+	PINGROUP(11, NORTH, blsp_spi3, blsp_i2c3, NA, dbg_out, wlan2_adc0,
+		 atest_usb10, bimc_dte0, NA, NA),
+	PINGROUP(12, NORTH, blsp_spi4, pri_mi2s, NA, phase_flag26, qdss_cti,
 		 NA, NA, NA, NA),
-	PINGROUP(13, SOUTH, blsp_spi4, pri_mi2s_ws, NA, phase_flag27,
-		 qdss_gpio5, NA, NA, NA, NA),
-	PINGROUP(14, SOUTH, blsp_spi4, blsp_i2c4, pri_mi2s, phase_flag28, NA,
+	PINGROUP(13, NORTH, blsp_spi4, DP_HOT, pri_mi2s_ws, NA, NA,
+		 phase_flag27, qdss_cti, NA, NA),
+	PINGROUP(14, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, phase_flag28,
 		 NA, NA, NA, NA),
-	PINGROUP(15, SOUTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, NA, NA, NA, NA,
+	PINGROUP(15, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(16, WEST, blsp_uart5, blsp_spi5, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(17, WEST, blsp_uart5, blsp_spi5, phase_flag5, NA, NA, NA, NA,
+	PINGROUP(16, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(18, WEST, blsp_uart5, blsp_spi5, blsp_i2c5, blsp_uim5, NA, NA,
-		 NA, NA, NA),
-	PINGROUP(19, WEST, blsp_uart5, blsp_spi5, blsp_i2c5, blsp_uim5, NA, NA,
-		 NA, NA, NA),
-	PINGROUP(20, WEST, blsp_spi6, blsp_uart2, NA, qdss_cti, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(21, WEST, blsp_spi6, blsp_uart2, phase_flag11, qdss_cti,
-		 vsense_data0, NA, NA, NA, NA),
-	PINGROUP(22, WEST, blsp_spi6, blsp_uart2, blsp_i2c6, blsp_uim6,
+	PINGROUP(17, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, phase_flag5,
+		 NA, NA, NA, NA),
+	PINGROUP(18, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(20, SOUTH, blsp_spi6, blsp_uart2, blsp_uim6, NA, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(21, SOUTH, blsp_spi6, blsp_uart2, blsp_uim6, NA, phase_flag11,
+		 qdss_cti, vsense_data0, NA, NA),
+	PINGROUP(22, CENTER, blsp_spi6, blsp_uart2, blsp_i2c6, NA,
 		 phase_flag12, vsense_data1, NA, NA, NA),
-	PINGROUP(23, WEST, blsp_spi6, blsp_uart2, blsp_i2c6, blsp_uim6,
+	PINGROUP(23, CENTER, blsp_spi6, blsp_uart2, blsp_i2c6, NA,
 		 phase_flag13, vsense_mode, NA, NA, NA),
-	PINGROUP(24, WEST, blsp_spi7, BLSP_UART, sec_mi2s, sndwire_clk, NA,
-		 phase_flag17, qdss_cti, vsense_clkout, NA),
-	PINGROUP(25, WEST, blsp_spi7, BLSP_UART, sec_mi2s, sndwire_data, NA,
-		 phase_flag18, qdss_cti, NA, NA),
-	PINGROUP(26, WEST, blsp_spi7, BLSP_UART, blsp_i2c7, sec_mi2s, wsa_en1,
-		 phase_flag19, qdss_cti, NA, NA),
-	PINGROUP(27, WEST, blsp_spi7, BLSP_UART, blsp_i2c7, vfr_1, sec_mi2s,
-		 wsa_en2, phase_flag20, NA, NA),
-	PINGROUP(28, SOUTH, blsp_spi, BLSP_UART, m_voc, phase_flag21, NA, NA,
+	PINGROUP(24, NORTH, blsp_spi7, BLSP_UART, sec_mi2s, sndwire_clk, NA,
+		 NA, phase_flag17, vsense_clkout, NA),
+	PINGROUP(25, NORTH, blsp_spi7, BLSP_UART, sec_mi2s, sndwire_data, NA,
+		 NA, phase_flag18, NA, NA),
+	PINGROUP(26, NORTH, blsp_spi7, BLSP_UART, blsp_i2c7, sec_mi2s, NA,
+		 phase_flag19, NA, NA, NA),
+	PINGROUP(27, NORTH, blsp_spi7, BLSP_UART, blsp_i2c7, vfr_1, sec_mi2s,
+		 NA, phase_flag20, NA, NA),
+	PINGROUP(28, CENTER, blsp_spi, BLSP_UART, m_voc, NA, phase_flag21, NA,
 		 NA, NA, NA),
-	PINGROUP(29, SOUTH, blsp_spi, BLSP_UART, NA, phase_flag22, NA, NA, NA,
+	PINGROUP(29, CENTER, blsp_spi, BLSP_UART, NA, NA, phase_flag22, NA, NA,
 		 NA, NA),
-	PINGROUP(30, SOUTH, blsp_spi, BLSP_UART, BLSP_I2C, blsp_spi3,
-		 phase_flag23, NA, NA, NA, NA),
-	PINGROUP(31, SOUTH, blsp_spi, BLSP_UART, BLSP_I2C, pwr_modem,
-		 phase_flag24, qdss_gpio, NA, NA, NA),
-	PINGROUP(32, SOUTH, cam_mclk, pwr_nav, NA, qdss_gpio0, NA, NA, NA, NA,
+	PINGROUP(30, CENTER, blsp_spi, BLSP_UART, BLSP_I2C, blsp_spi3, NA,
+		 phase_flag23, NA, NA, NA),
+	PINGROUP(31, CENTER, blsp_spi, BLSP_UART, BLSP_I2C, pwr_modem, NA,
+		 phase_flag24, qdss_gpio, NA, NA),
+	PINGROUP(32, SOUTH, cam_mclk, pwr_nav, NA, NA, qdss_gpio0, NA, NA, NA,
 		 NA),
-	PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, NA, qdss_gpio1,
-		 NA, NA, NA, NA),
-	PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, NA, qdss_gpio2,
-		 NA, NA, NA, NA),
-	PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, NA, qdss_gpio3,
-		 NA, NA, NA, NA),
-	PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, NA, qdss_gpio4,
-		 atest_tsens, NA, NA, NA),
-	PINGROUP(37, SOUTH, cci_i2c, pll_reset, NA, qdss_gpio5, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(38, SOUTH, cci_i2c, NA, qdss_gpio6, NA, NA, NA, NA, NA, NA),
-	PINGROUP(39, SOUTH, cci_i2c, NA, qdss_gpio7, NA, NA, NA, NA, NA, NA),
-	PINGROUP(40, SOUTH, CCI_TIMER0, NA, blsp_spi, NA, qdss_gpio8, NA, NA,
-		 NA, NA),
-	PINGROUP(41, SOUTH, CCI_TIMER1, NA, blsp_spi, NA, qdss_gpio, NA, NA,
-		 NA, NA),
+	PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, NA, NA,
+		 qdss_gpio1, NA, NA, NA),
+	PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, NA, NA,
+		 qdss_gpio2, NA, NA, NA),
+	PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, NA, NA,
+		 qdss_gpio3, NA, atest_usb2, NA),
+	PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, NA, NA,
+		 qdss_gpio4, atest_tsens, atest_usb21, NA),
+	PINGROUP(37, SOUTH, cci_i2c, pll_reset, NA, NA, qdss_gpio5,
+		 atest_usb23, NA, NA, NA),
+	PINGROUP(38, SOUTH, cci_i2c, NA, NA, qdss_gpio6, NA, NA, NA, NA, NA),
+	PINGROUP(39, SOUTH, cci_i2c, NA, NA, qdss_gpio7, NA, NA, NA, NA, NA),
+	PINGROUP(40, SOUTH, CCI_TIMER0, NA, blsp_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(41, SOUTH, CCI_TIMER1, NA, blsp_spi, NA, NA, NA, NA, NA, NA),
 	PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3,
-		 NA, qdss_gpio9, NA, NA, NA),
-	PINGROUP(43, SOUTH, CCI_TIMER3, CCI_ASYNC, qspi_cs, NA, qdss_gpio10,
-		 NA, NA, NA, NA),
-	PINGROUP(44, SOUTH, CCI_TIMER4, CCI_ASYNC, blsp_spi, BLSP_I2C, NA,
-		 qdss_gpio11, NA, NA, NA),
-	PINGROUP(45, SOUTH, cci_async, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA),
-	PINGROUP(46, SOUTH, blsp_spi1, NA, qdss_gpio13, NA, NA, NA, NA, NA, NA),
-	PINGROUP(47, SOUTH, qspi_clk, phase_flag30, qdss_gpio14, NA, NA, NA,
-		 NA, NA, NA),
-	PINGROUP(48, SOUTH, qspi_resetn, phase_flag1, qdss_gpio15, NA, NA, NA,
+		 NA, NA, qdss_gpio9, NA, NA),
+	PINGROUP(43, SOUTH, CCI_TIMER3, CCI_ASYNC, qspi_cs, NA, NA,
+		 qdss_gpio10, NA, NA, NA),
+	PINGROUP(44, SOUTH, CCI_TIMER4, CCI_ASYNC, blsp_spi, BLSP_I2C, NA, NA,
+		 qdss_gpio11, NA, NA),
+	PINGROUP(45, SOUTH, cci_async, NA, NA, qdss_gpio12, NA, NA, NA, NA, NA),
+	PINGROUP(46, SOUTH, blsp_spi1, NA, NA, qdss_gpio13, NA, NA, NA, NA, NA),
+	PINGROUP(47, SOUTH, qspi_clk, NA, phase_flag30, qdss_gpio14, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(49, SOUTH, phase_flag2, qdss_cti, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(50, SOUTH, qspi_cs, phase_flag9, qdss_cti, NA, NA, NA, NA, NA,
+	PINGROUP(48, SOUTH, NA, phase_flag1, qdss_gpio15, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(51, SOUTH, qspi_data3, phase_flag15, NA, NA, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(52, EAST, CCI_TIMER2, blsp_spi, BLSP_I2C, phase_flag16, NA,
-		 NA, NA, NA, NA),
-	PINGROUP(53, EAST, phase_flag6, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(54, EAST, NA, phase_flag29, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(55, WEST, phase_flag25, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(56, WEST, phase_flag10, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(57, SOUTH, gcc_gp1, phase_flag4, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(58, SOUTH, USB_PHY, gcc_gp2, NA, atest_char, NA, NA, NA, NA,
+	PINGROUP(49, SOUTH, NA, phase_flag2, qdss_cti, NA, NA, NA, NA, NA, NA),
+	PINGROUP(50, SOUTH, qspi_cs, NA, phase_flag9, qdss_cti, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(59, EAST, mdp_vsync, gcc_gp3, NA, atest_char3, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(60, EAST, EDP_HOT, cri_trng0, NA, atest_char2, NA, NA, NA, NA,
-		 NA),
-	PINGROUP(61, EAST, pri_mi2s, cri_trng1, NA, qdss_cti, atest_char1, NA,
+	PINGROUP(51, SOUTH, qspi_data3, NA, phase_flag15, qdss_gpio8, NA, NA,
+		 NA, NA, NA),
+	PINGROUP(52, SOUTH, CCI_TIMER2, blsp_spi, BLSP_I2C, NA, phase_flag16,
+		 qdss_gpio, NA, NA, NA),
+	PINGROUP(53, NORTH, NA, phase_flag6, qdss_cti, NA, NA, NA, NA, NA, NA),
+	PINGROUP(54, NORTH, NA, NA, phase_flag29, NA, NA, NA, NA, NA, NA),
+	PINGROUP(55, SOUTH, NA, phase_flag25, qdss_cti, NA, NA, NA, NA, NA, NA),
+	PINGROUP(56, SOUTH, NA, phase_flag10, qdss_gpio3, NA, atest_usb20, NA,
 		 NA, NA, NA),
-	PINGROUP(62, SOUTH, sec_mi2s, audio_ref, MDP_VSYNC, cri_trng, NA,
-		 qdss_gpio0, atest_char0, NA, NA),
-	PINGROUP(63, SOUTH, NA, NA, qdss_gpio1, NA, NA, NA, NA, NA, NA),
-	PINGROUP(64, SOUTH, NAV_PPS, blsp_spi8, sp_cmu, NA, qdss_gpio2, NA, NA,
+	PINGROUP(57, SOUTH, gcc_gp1, NA, phase_flag4, atest_usb22, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(65, SOUTH, NAV_PPS, blsp_spi3, NA, adsp_ext, NA, qdss_gpio3,
+	PINGROUP(58, SOUTH, USB_PHY, gcc_gp2, NA, NA, atest_char, NA, NA, NA,
+		 NA),
+	PINGROUP(59, NORTH, mdp_vsync, gcc_gp3, NA, NA, atest_char3, NA, NA,
+		 NA, NA),
+	PINGROUP(60, NORTH, cri_trng0, NA, NA, atest_char2, NA, NA, NA, NA, NA),
+	PINGROUP(61, NORTH, pri_mi2s, cri_trng1, NA, NA, atest_char1, NA, NA,
+		 NA, NA),
+	PINGROUP(62, NORTH, sec_mi2s, audio_ref, MDP_VSYNC, cri_trng, NA, NA,
+		 atest_char0, NA, NA),
+	PINGROUP(63, NORTH, NA, NA, NA, qdss_gpio1, NA, NA, NA, NA, NA),
+	PINGROUP(64, SOUTH, blsp_spi8, sp_cmu, NA, NA, qdss_gpio2, NA, NA, NA,
+		 NA),
+	PINGROUP(65, SOUTH, NA, NAV_PPS, NAV_PPS, GPS_TX, blsp_spi3, adsp_ext,
 		 NA, NA, NA),
-	PINGROUP(66, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(67, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(68, SOUTH, isense_dbg, phase_flag0, qdss_gpio, NA, NA, NA, NA,
+	PINGROUP(66, NORTH, NA, NA, qdss_cti, NA, NA, NA, NA, NA, NA),
+	PINGROUP(67, NORTH, NA, NA, qdss_gpio0, NA, NA, NA, NA, NA, NA),
+	PINGROUP(68, NORTH, isense_dbg, NA, phase_flag0, qdss_gpio, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(69, SOUTH, phase_flag7, qdss_gpio, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(70, SOUTH, phase_flag8, qdss_gpio6, NA, NA, NA, NA, NA, NA,
+	PINGROUP(69, NORTH, NA, phase_flag7, qdss_gpio, NA, NA, NA, NA, NA, NA),
+	PINGROUP(70, NORTH, NA, phase_flag8, qdss_gpio6, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(71, SOUTH, NA, qdss_gpio7, tsense_pwm1, tsense_pwm2, NA, NA,
+	PINGROUP(71, NORTH, NA, NA, qdss_gpio7, tsense_pwm1, tsense_pwm2, NA,
 		 NA, NA, NA),
-	PINGROUP(72, SOUTH, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(73, SOUTH, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(74, SOUTH, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(75, WEST, NA, qdss_gpio8, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(76, WEST, blsp_spi8, NA, NA, qdss_gpio9, NA, NA, NA, NA, NA),
-	PINGROUP(77, SOUTH, NA, qdss_gpio10, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(78, SOUTH, gcc_gp1, qdss_gpio13, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(79, SOUTH, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(80, SOUTH, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(81, SOUTH, mss_lte, gcc_gp2, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(82, SOUTH, mss_lte, NA, gcc_gp3, NA, NA, NA, NA, NA, NA),
+	PINGROUP(72, NORTH, NA, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(73, NORTH, NA, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA),
+	PINGROUP(74, NORTH, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(75, NORTH, NA, NA, qdss_gpio8, NA, NA, NA, NA, NA, NA),
+	PINGROUP(76, NORTH, blsp_spi8, NA, NA, NA, qdss_gpio9, NA, NA, NA, NA),
+	PINGROUP(77, NORTH, NA, NA, qdss_gpio10, NA, NA, NA, NA, NA, NA),
+	PINGROUP(78, NORTH, gcc_gp1, NA, qdss_gpio13, NA, NA, NA, NA, NA, NA),
+	PINGROUP(79, SOUTH, NA, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA),
+	PINGROUP(80, SOUTH, NAV_PPS, NAV_PPS, GPS_TX, NA, NA, qdss_gpio12, NA,
+		 NA, NA),
+	PINGROUP(81, CENTER, mss_lte, gcc_gp2, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(82, CENTER, mss_lte, gcc_gp3, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(83, SOUTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(84, SOUTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(85, SOUTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -1502,12 +1569,12 @@ static const struct msm_pingroup msmfalcon_groups[] = {
 	PINGROUP(91, SOUTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(92, SOUTH, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA),
 	PINGROUP(93, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(94, SOUTH, NA, ssbi_gnss, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(94, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(95, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(96, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(97, SOUTH, NA, NA, ldo_en, NA, NA, NA, NA, NA, NA),
-	PINGROUP(98, SOUTH, NA, NAV_PPS, NAV_PPS, ldo_update, NA, NA, NA, NA,
-		 NA),
+	PINGROUP(97, SOUTH, NA, ldo_en, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(98, SOUTH, NA, NAV_PPS, NAV_PPS, GPS_TX, ldo_update, NA, NA,
+		 NA, NA),
 	PINGROUP(99, SOUTH, qlink_request, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(100, SOUTH, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(101, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -1516,10 +1583,13 @@ static const struct msm_pingroup msmfalcon_groups[] = {
 	PINGROUP(104, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(105, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(106, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(107, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(108, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(109, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(110, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(107, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(108, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(109, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(110, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(111, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(112, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(113, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	SDC_QDSD_PINGROUP(sdc1_clk, 0x99a000, 13, 6),
 	SDC_QDSD_PINGROUP(sdc1_cmd, 0x99a000, 11, 3),
 	SDC_QDSD_PINGROUP(sdc1_data, 0x99a000, 9, 0),
@@ -1536,7 +1606,7 @@ static const struct msm_pinctrl_soc_data msmfalcon_pinctrl = {
 	.nfunctions = ARRAY_SIZE(msmfalcon_functions),
 	.groups = msmfalcon_groups,
 	.ngroups = ARRAY_SIZE(msmfalcon_groups),
-	.ngpios = 111,
+	.ngpios = 114,
 };
 
 static int msmfalcon_pinctrl_probe(struct platform_device *pdev)