msm: kgsl: Purge unused #defines

Remove unused #defines, structs and members that are no longer used.

CRs-Fixed: 971156
Change-Id: Ibdf6fef6f3f700f3c5315c228c0473e47fb62163
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

19 files changed, 7 insertions, 637 deletions

diff --git a/drivers/gpu/msm/a3xx_reg.h b/drivers/gpu/msm/a3xx_reg.h
index d8f94757ba28..fd972dfd3862 100644
--- a/drivers/gpu/msm/a3xx_reg.h
+++ b/drivers/gpu/msm/a3xx_reg.h
@@ -44,35 +44,20 @@
 /* CP_EVENT_WRITE events */
 #define CACHE_FLUSH_TS 4
 
-/* CP_INTERRUPT masks */
-
-#define CP_INTERRUPT_IB2 0x20000000
-#define CP_INTERRUPT_IB1 0x40000000
-#define CP_INTERRUPT_RB  0x80000000
-
 /* Register definitions */
 
-#define A3XX_RBBM_HW_VERSION 0x000
-#define A3XX_RBBM_HW_RELEASE 0x001
-#define A3XX_RBBM_HW_CONFIGURATION 0x002
 #define A3XX_RBBM_CLOCK_CTL 0x010
 #define A3XX_RBBM_SP_HYST_CNT 0x012
 #define A3XX_RBBM_SW_RESET_CMD 0x018
 #define A3XX_RBBM_AHB_CTL0 0x020
 #define A3XX_RBBM_AHB_CTL1 0x021
 #define A3XX_RBBM_AHB_CMD 0x022
-#define A3XX_RBBM_AHB_ME_SPLIT_STATUS 0x25
-#define A3XX_RBBM_AHB_PFP_SPLIT_STATUS 0x26
 #define A3XX_RBBM_AHB_ERROR_STATUS 0x027
 #define A3XX_RBBM_GPR0_CTL 0x02E
 /* This the same register as on A2XX, just in a different place */
 #define A3XX_RBBM_STATUS 0x030
 #define A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x33
 #define A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x50
-#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x51
-#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x54
-#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x57
-#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x5A
 #define A3XX_RBBM_INT_CLEAR_CMD 0x061
 #define A3XX_RBBM_INT_0_MASK 0x063
 #define A3XX_RBBM_INT_0_STATUS 0x064
@@ -188,10 +173,8 @@
 #define A3XX_RBBM_EXT_TRACE_CMD 0x122
 #define A3XX_CP_RB_BASE 0x01C0
 #define A3XX_CP_RB_CNTL 0x01C1
-#define A3XX_CP_RB_RPTR_ADDR 0x01C3
 #define A3XX_CP_RB_RPTR 0x01C4
 #define A3XX_CP_RB_WPTR 0x01C5
-#define A3XX_CP_RB_RPTR_WR 0x01C7
 /* Following two are same as on A2XX, just in a different place */
 #define A3XX_CP_PFP_UCODE_ADDR 0x1C9
 #define A3XX_CP_PFP_UCODE_DATA 0x1CA
@@ -203,8 +186,6 @@
 #define A3XX_CP_QUEUE_THRESHOLDS 0x01D5
 #define A3XX_CP_MEQ_ADDR 0x1DA
 #define A3XX_CP_MEQ_DATA 0x1DB
-#define A3XX_CP_SCRATCH_UMSK 0x01DC
-#define A3XX_CP_SCRATCH_ADDR 0x01DD
 #define A3XX_CP_STATE_DEBUG_INDEX 0x01EC
 #define A3XX_CP_STATE_DEBUG_DATA 0x01ED
 #define A3XX_CP_CNTL 0x01F4
@@ -225,53 +206,28 @@
 #define A3XX_CP_IB2_BUFSZ 0x045B
 
 #define A3XX_CP_HW_FAULT  0x45C
-#define A3XX_CP_AHB_FAULT 0x54D
 #define A3XX_CP_PROTECT_CTRL 0x45E
 #define A3XX_CP_PROTECT_STATUS 0x45F
 #define A3XX_CP_PROTECT_REG_0 0x460
-#define A3XX_CP_PROTECT_REG_1 0x461
-#define A3XX_CP_PROTECT_REG_2 0x462
-#define A3XX_CP_PROTECT_REG_3 0x463
-#define A3XX_CP_PROTECT_REG_4 0x464
-#define A3XX_CP_PROTECT_REG_5 0x465
-#define A3XX_CP_PROTECT_REG_6 0x466
-#define A3XX_CP_PROTECT_REG_7 0x467
-#define A3XX_CP_PROTECT_REG_8 0x468
-#define A3XX_CP_PROTECT_REG_9 0x469
-#define A3XX_CP_PROTECT_REG_A 0x46A
-#define A3XX_CP_PROTECT_REG_B 0x46B
-#define A3XX_CP_PROTECT_REG_C 0x46C
-#define A3XX_CP_PROTECT_REG_D 0x46D
-#define A3XX_CP_PROTECT_REG_E 0x46E
-#define A3XX_CP_PROTECT_REG_F 0x46F
 #define A3XX_CP_STAT 0x047F
 #define A3XX_CP_SCRATCH_REG0 0x578
 #define A3XX_CP_SCRATCH_REG6 0x57E
 #define A3XX_CP_SCRATCH_REG7 0x57F
-#define A3XX_VSC_BIN_SIZE 0xC01
 #define A3XX_VSC_SIZE_ADDRESS 0xC02
-#define A3XX_VSC_PIPE_CONFIG_0 0xC06
 #define A3XX_VSC_PIPE_DATA_ADDRESS_0 0xC07
 #define A3XX_VSC_PIPE_DATA_LENGTH_0 0xC08
-#define A3XX_VSC_PIPE_CONFIG_1 0xC09
 #define A3XX_VSC_PIPE_DATA_ADDRESS_1 0xC0A
 #define A3XX_VSC_PIPE_DATA_LENGTH_1 0xC0B
-#define A3XX_VSC_PIPE_CONFIG_2 0xC0C
 #define A3XX_VSC_PIPE_DATA_ADDRESS_2 0xC0D
 #define A3XX_VSC_PIPE_DATA_LENGTH_2 0xC0E
-#define A3XX_VSC_PIPE_CONFIG_3 0xC0F
 #define A3XX_VSC_PIPE_DATA_ADDRESS_3 0xC10
 #define A3XX_VSC_PIPE_DATA_LENGTH_3 0xC11
-#define A3XX_VSC_PIPE_CONFIG_4 0xC12
 #define A3XX_VSC_PIPE_DATA_ADDRESS_4 0xC13
 #define A3XX_VSC_PIPE_DATA_LENGTH_4 0xC14
-#define A3XX_VSC_PIPE_CONFIG_5 0xC15
 #define A3XX_VSC_PIPE_DATA_ADDRESS_5 0xC16
 #define A3XX_VSC_PIPE_DATA_LENGTH_5 0xC17
-#define A3XX_VSC_PIPE_CONFIG_6 0xC18
 #define A3XX_VSC_PIPE_DATA_ADDRESS_6 0xC19
 #define A3XX_VSC_PIPE_DATA_LENGTH_6 0xC1A
-#define A3XX_VSC_PIPE_CONFIG_7 0xC1B
 #define A3XX_VSC_PIPE_DATA_ADDRESS_7 0xC1C
 #define A3XX_VSC_PIPE_DATA_LENGTH_7 0xC1D
 #define A3XX_PC_PERFCOUNTER0_SELECT 0xC48
@@ -417,10 +373,6 @@
 #define A3XX_RB_SAMPLE_COUNT_ADDR 0x2111
 #define A3XX_RB_Z_CLAMP_MIN 0x2114
 #define A3XX_RB_Z_CLAMP_MAX 0x2115
-#define A3XX_PC_VSTREAM_CONTROL 0x21E4
-#define A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x21EA
-#define A3XX_PC_PRIM_VTX_CNTL 0x21EC
-#define A3XX_PC_RESTART_INDEX 0x21ED
 #define A3XX_HLSQ_CONTROL_0_REG 0x2200
 #define A3XX_HLSQ_CONTROL_1_REG 0x2201
 #define A3XX_HLSQ_CONTROL_2_REG 0x2202
@@ -443,11 +395,6 @@
 #define A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x2216
 #define A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x2217
 #define A3XX_HLSQ_CL_WG_OFFSET_REG 0x221A
-#define A3XX_VFD_CONTROL_0 0x2240
-#define A3XX_VFD_INDEX_MIN 0x2242
-#define A3XX_VFD_INDEX_MAX 0x2243
-#define A3XX_VFD_FETCH_INSTR_0_0 0x2246
-#define A3XX_VFD_FETCH_INSTR_0_4 0x224E
 #define A3XX_VFD_FETCH_INSTR_1_0 0x2247
 #define A3XX_VFD_FETCH_INSTR_1_1 0x2249
 #define A3XX_VFD_FETCH_INSTR_1_2 0x224B
@@ -464,10 +411,6 @@
 #define A3XX_VFD_FETCH_INSTR_1_D 0x2261
 #define A3XX_VFD_FETCH_INSTR_1_E 0x2263
 #define A3XX_VFD_FETCH_INSTR_1_F 0x2265
-#define A3XX_VFD_DECODE_INSTR_0 0x2266
-#define A3XX_VFD_VS_THREADING_THRESHOLD 0x227E
-#define A3XX_VPC_ATTR 0x2280
-#define A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x228B
 #define A3XX_SP_SP_CTRL_REG 0x22C0
 #define A3XX_SP_VS_CTRL_REG0 0x22C4
 #define A3XX_SP_VS_CTRL_REG1 0x22C5
@@ -510,13 +453,7 @@
 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_3 0x22F7
 #define A3XX_SP_FS_LENGTH_REG 0x22FF
 #define A3XX_PA_SC_AA_CONFIG 0x2301
-#define A3XX_TPL1_TP_VS_TEX_OFFSET 0x2340
-#define A3XX_TPL1_TP_FS_TEX_OFFSET 0x2342
-#define A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x2343
 #define A3XX_VBIF_CLKON 0x3001
-#define A3XX_VBIF_FIXED_SORT_EN 0x300C
-#define A3XX_VBIF_FIXED_SORT_SEL0 0x300D
-#define A3XX_VBIF_FIXED_SORT_SEL1 0x300E
 #define A3XX_VBIF_ABIT_SORT 0x301C
 #define A3XX_VBIF_ABIT_SORT_CONF 0x301D
 #define A3XX_VBIF_GATE_OFF_WRREQ_EN 0x302A
@@ -529,12 +466,8 @@
 #define A3XX_VBIF_DDR_OUT_MAX_BURST 0x3036
 #define A3XX_VBIF_ARB_CTL 0x303C
 #define A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x3049
-#define A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x3058
 #define A3XX_VBIF_OUT_AXI_AOOO_EN 0x305E
 #define A3XX_VBIF_OUT_AXI_AOOO 0x305F
-#define A3XX_VBIF_PERF_CNT_EN 0x3070
-#define A3XX_VBIF_PERF_CNT_CLR 0x3071
-#define A3XX_VBIF_PERF_CNT_SEL 0x3072
 #define A3XX_VBIF_PERF_CNT0_LO 0x3073
 #define A3XX_VBIF_PERF_CNT0_HI 0x3074
 #define A3XX_VBIF_PERF_CNT1_LO 0x3075
@@ -553,14 +486,6 @@
 #define A3XX_VBIF_XIN_HALT_CTRL1 0x3081
 
 /* VBIF register offsets for A306 */
-#define A3XX_VBIF2_PERF_CNT_EN0 0x30c0
-#define A3XX_VBIF2_PERF_CNT_EN1 0x30c1
-#define A3XX_VBIF2_PERF_CNT_EN2 0x30c2
-#define A3XX_VBIF2_PERF_CNT_EN3 0x30c3
-#define A3XX_VBIF2_PERF_CNT_CLR0 0x30c8
-#define A3XX_VBIF2_PERF_CNT_CLR1 0x30c9
-#define A3XX_VBIF2_PERF_CNT_CLR2 0x30ca
-#define A3XX_VBIF2_PERF_CNT_CLR3 0x30cb
 #define A3XX_VBIF2_PERF_CNT_SEL0 0x30d0
 #define A3XX_VBIF2_PERF_CNT_SEL1 0x30d1
 #define A3XX_VBIF2_PERF_CNT_SEL2 0x30d2
@@ -577,9 +502,6 @@
 #define A3XX_VBIF2_PERF_PWR_CNT_EN0 0x3100
 #define A3XX_VBIF2_PERF_PWR_CNT_EN1 0x3101
 #define A3XX_VBIF2_PERF_PWR_CNT_EN2 0x3102
-#define A3XX_VBIF2_PERF_PWR_CNT_CLR0 0x3108
-#define A3XX_VBIF2_PERF_PWR_CNT_CLR1 0x3109
-#define A3XX_VBIF2_PERF_PWR_CNT_CLR2 0x310A
 #define A3XX_VBIF2_PERF_PWR_CNT_LOW0 0x3110
 #define A3XX_VBIF2_PERF_PWR_CNT_LOW1 0x3111
 #define A3XX_VBIF2_PERF_PWR_CNT_LOW2 0x3112
@@ -590,240 +512,7 @@
 #define A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL0 0x3800
 #define A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL1 0x3801
 
-/* Various flags used by the context switch code */
-
-#define SP_MULTI 0
-#define SP_BUFFER_MODE 1
-#define SP_TWO_VTX_QUADS 0
-#define SP_PIXEL_BASED 0
-#define SP_R8G8B8A8_UNORM 8
-#define SP_FOUR_PIX_QUADS 1
-
-#define HLSQ_DIRECT 0
-#define HLSQ_BLOCK_ID_SP_VS 4
-#define HLSQ_SP_VS_INSTR 0
-#define HLSQ_SP_FS_INSTR 0
-#define HLSQ_BLOCK_ID_SP_FS 6
-#define HLSQ_TWO_PIX_QUADS 0
-#define HLSQ_TWO_VTX_QUADS 0
-#define HLSQ_BLOCK_ID_TP_TEX 2
-#define HLSQ_TP_TEX_SAMPLERS 0
-#define HLSQ_TP_TEX_MEMOBJ 1
-#define HLSQ_BLOCK_ID_TP_MIPMAP 3
-#define HLSQ_TP_MIPMAP_BASE 1
-#define HLSQ_FOUR_PIX_QUADS 1
-
-#define RB_FACTOR_ONE 1
-#define RB_BLEND_OP_ADD 0
-#define RB_FACTOR_ZERO 0
-#define RB_DITHER_DISABLE 0
-#define RB_DITHER_ALWAYS 1
-#define RB_FRAG_NEVER 0
-#define RB_ENDIAN_NONE 0
-#define RB_R8G8B8A8_UNORM 8
-#define RB_RESOLVE_PASS 2
-#define RB_CLEAR_MODE_RESOLVE 1
-#define RB_TILINGMODE_LINEAR 0
-#define RB_REF_NEVER 0
-#define RB_FRAG_LESS 1
-#define RB_REF_ALWAYS 7
-#define RB_STENCIL_KEEP 0
-#define RB_RENDERING_PASS 0
-#define RB_TILINGMODE_32X32 2
-
-#define PC_DRAW_TRIANGLES 2
-#define PC_DI_PT_RECTLIST 8
-#define PC_DI_SRC_SEL_AUTO_INDEX 2
-#define PC_DI_INDEX_SIZE_16_BIT 0
-#define PC_DI_IGNORE_VISIBILITY 0
-#define PC_DI_PT_TRILIST 4
-#define PC_DI_SRC_SEL_IMMEDIATE 1
-#define PC_DI_INDEX_SIZE_32_BIT 1
-
-#define UCHE_ENTIRE_CACHE 1
-#define UCHE_OP_INVALIDATE 1
-
-/*
- * The following are bit field shifts within some of the registers defined
- * above. These are used in the context switch code in conjunction with the
- * _SET macro
- */
-
-#define GRAS_CL_CLIP_CNTL_CLIP_DISABLE 16
-#define GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 12
-#define GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 21
-#define GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 19
-#define GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 20
-#define GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 17
-#define GRAS_CL_VPORT_XSCALE_VPORT_XSCALE 0
-#define GRAS_CL_VPORT_YSCALE_VPORT_YSCALE 0
-#define GRAS_CL_VPORT_ZSCALE_VPORT_ZSCALE 0
-#define GRAS_SC_CONTROL_RASTER_MODE 12
-#define GRAS_SC_CONTROL_RENDER_MODE 4
-#define GRAS_SC_SCREEN_SCISSOR_BR_BR_X 0
-#define GRAS_SC_SCREEN_SCISSOR_BR_BR_Y 16
-#define GRAS_SC_WINDOW_SCISSOR_BR_BR_X 0
-#define GRAS_SC_WINDOW_SCISSOR_BR_BR_Y 16
-#define GRAS_SU_CTRLMODE_LINEHALFWIDTH 03
-#define HLSQ_CONSTFSPRESERVEDRANGEREG_ENDENTRY 16
-#define HLSQ_CONSTFSPRESERVEDRANGEREG_STARTENTRY 0
-#define HLSQ_CTRL0REG_CHUNKDISABLE 26
-#define HLSQ_CTRL0REG_CONSTSWITCHMODE 27
-#define HLSQ_CTRL0REG_FSSUPERTHREADENABLE 6
-#define HLSQ_CTRL0REG_FSTHREADSIZE 4
-#define HLSQ_CTRL0REG_LAZYUPDATEDISABLE 28
-#define HLSQ_CTRL0REG_RESERVED2 10
-#define HLSQ_CTRL0REG_SPCONSTFULLUPDATE 29
-#define HLSQ_CTRL0REG_SPSHADERRESTART 9
-#define HLSQ_CTRL0REG_TPFULLUPDATE 30
-#define HLSQ_CTRL1REG_RESERVED1 9
-#define HLSQ_CTRL1REG_VSSUPERTHREADENABLE 8
-#define HLSQ_CTRL1REG_VSTHREADSIZE 6
-#define HLSQ_CTRL2REG_PRIMALLOCTHRESHOLD 26
-#define HLSQ_FSCTRLREG_FSCONSTLENGTH 0
-#define HLSQ_FSCTRLREG_FSCONSTSTARTOFFSET 12
-#define HLSQ_FSCTRLREG_FSINSTRLENGTH 24
-#define HLSQ_VSCTRLREG_VSINSTRLENGTH 24
-#define PC_PRIM_VTX_CONTROL_POLYMODE_BACK_PTYPE 8
-#define PC_PRIM_VTX_CONTROL_POLYMODE_FRONT_PTYPE 5
-#define PC_PRIM_VTX_CONTROL_PROVOKING_VTX_LAST 25
-#define PC_PRIM_VTX_CONTROL_STRIDE_IN_VPC 0
-#define PC_DRAW_INITIATOR_PRIM_TYPE 0
-#define PC_DRAW_INITIATOR_SOURCE_SELECT 6
-#define PC_DRAW_INITIATOR_VISIBILITY_CULLING_MODE 9
-#define PC_DRAW_INITIATOR_INDEX_SIZE 0x0B
-#define PC_DRAW_INITIATOR_SMALL_INDEX 0x0D
-#define PC_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x0E
-#define RB_COPYCONTROL_COPY_GMEM_BASE 14
-#define RB_COPYCONTROL_RESOLVE_CLEAR_MODE 4
-#define RB_COPYDESTBASE_COPY_DEST_BASE 4
-#define RB_COPYDESTINFO_COPY_COMPONENT_ENABLE 14
-#define RB_COPYDESTINFO_COPY_DEST_ENDIAN 18
-#define RB_COPYDESTINFO_COPY_DEST_FORMAT 2
-#define RB_COPYDESTINFO_COPY_DEST_TILE 0
-#define RB_COPYDESTPITCH_COPY_DEST_PITCH 0
-#define RB_DEPTHCONTROL_Z_TEST_FUNC 4
-#define RB_MODECONTROL_RENDER_MODE 8
-#define RB_MODECONTROL_MARB_CACHE_SPLIT_MODE 15
-#define RB_MODECONTROL_PACKER_TIMER_ENABLE 16
-#define RB_MRTBLENDCONTROL_ALPHA_BLEND_OPCODE 21
-#define RB_MRTBLENDCONTROL_ALPHA_DEST_FACTOR 24
-#define RB_MRTBLENDCONTROL_ALPHA_SRC_FACTOR 16
-#define RB_MRTBLENDCONTROL_CLAMP_ENABLE 29
-#define RB_MRTBLENDCONTROL_RGB_BLEND_OPCODE 5
-#define RB_MRTBLENDCONTROL_RGB_DEST_FACTOR 8
-#define RB_MRTBLENDCONTROL_RGB_SRC_FACTOR 0
-#define RB_MRTBUFBASE_COLOR_BUF_BASE 4
-#define RB_MRTBUFINFO_COLOR_BUF_PITCH 17
-#define RB_MRTBUFINFO_COLOR_FORMAT 0
-#define RB_MRTBUFINFO_COLOR_TILE_MODE 6
-#define RB_MRTCONTROL_COMPONENT_ENABLE 24
-#define RB_MRTCONTROL_DITHER_MODE 12
-#define RB_MRTCONTROL_READ_DEST_ENABLE 3
-#define RB_MRTCONTROL_ROP_CODE 8
-#define RB_MSAACONTROL_MSAA_DISABLE 10
-#define RB_MSAACONTROL_SAMPLE_MASK 16
-#define RB_RENDERCONTROL_ALPHA_TEST_FUNC 24
-#define RB_RENDERCONTROL_BIN_WIDTH 4
-#define RB_RENDERCONTROL_DISABLE_COLOR_PIPE 12
-#define RB_STENCILCONTROL_STENCIL_FAIL 11
-#define RB_STENCILCONTROL_STENCIL_FAIL_BF 23
-#define RB_STENCILCONTROL_STENCIL_FUNC 8
-#define RB_STENCILCONTROL_STENCIL_FUNC_BF 20
-#define RB_STENCILCONTROL_STENCIL_ZFAIL 17
-#define RB_STENCILCONTROL_STENCIL_ZFAIL_BF 29
-#define RB_STENCILCONTROL_STENCIL_ZPASS 14
-#define RB_STENCILCONTROL_STENCIL_ZPASS_BF 26
-#define SP_FSCTRLREG0_FSFULLREGFOOTPRINT 10
-#define SP_FSCTRLREG0_FSHALFREGFOOTPRINT 4
-#define SP_FSCTRLREG0_FSICACHEINVALID 2
-#define SP_FSCTRLREG0_FSINOUTREGOVERLAP 18
-#define SP_FSCTRLREG0_FSINSTRBUFFERMODE 1
-#define SP_FSCTRLREG0_FSLENGTH 24
-#define SP_FSCTRLREG0_FSSUPERTHREADMODE 21
-#define SP_FSCTRLREG0_FSTHREADMODE 0
-#define SP_FSCTRLREG0_FSTHREADSIZE 20
-#define SP_FSCTRLREG0_PIXLODENABLE 22
-#define SP_FSCTRLREG1_FSCONSTLENGTH 0
-#define SP_FSCTRLREG1_FSINITIALOUTSTANDING 20
-#define SP_FSCTRLREG1_HALFPRECVAROFFSET 24
-#define SP_FSMRTREG_REGID 0
-#define SP_FSMRTREG_PRECISION 8
-#define SP_FSOUTREG_PAD0 2
-#define SP_IMAGEOUTPUTREG_MRTFORMAT 0
-#define SP_IMAGEOUTPUTREG_DEPTHOUTMODE 3
-#define SP_IMAGEOUTPUTREG_PAD0 6
-#define SP_OBJOFFSETREG_CONSTOBJECTSTARTOFFSET 16
-#define SP_OBJOFFSETREG_SHADEROBJOFFSETINIC 25
-#define SP_SHADERLENGTH_LEN 0
-#define SP_SPCTRLREG_CONSTMODE 18
-#define SP_SPCTRLREG_LOMODE 22
-#define SP_SPCTRLREG_SLEEPMODE 20
-#define SP_VSCTRLREG0_VSFULLREGFOOTPRINT 10
-#define SP_VSCTRLREG0_VSICACHEINVALID 2
-#define SP_VSCTRLREG0_VSINSTRBUFFERMODE 1
-#define SP_VSCTRLREG0_VSLENGTH 24
-#define SP_VSCTRLREG0_VSSUPERTHREADMODE 21
-#define SP_VSCTRLREG0_VSTHREADMODE 0
-#define SP_VSCTRLREG0_VSTHREADSIZE 20
-#define SP_VSCTRLREG1_VSINITIALOUTSTANDING 24
-#define SP_VSOUTREG_COMPMASK0 9
-#define SP_VSPARAMREG_POSREGID 0
-#define SP_VSPARAMREG_PSIZEREGID 8
-#define SP_VSPARAMREG_TOTALVSOUTVAR 20
-#define SP_VSVPCDSTREG_OUTLOC0 0
-#define TPL1_TPTEXOFFSETREG_BASETABLEPTR 16
-#define TPL1_TPTEXOFFSETREG_MEMOBJOFFSET 8
-#define TPL1_TPTEXOFFSETREG_SAMPLEROFFSET 0
-#define UCHE_INVALIDATE1REG_OPCODE 0x1C
-#define UCHE_INVALIDATE1REG_ALLORPORTION 0x1F
-#define VFD_BASEADDR_BASEADDR 0
-#define VFD_CTRLREG0_PACKETSIZE 18
-#define VFD_CTRLREG0_STRMDECINSTRCNT 22
-#define VFD_CTRLREG0_STRMFETCHINSTRCNT 27
-#define VFD_CTRLREG0_TOTALATTRTOVS 0
-#define VFD_CTRLREG1_MAXSTORAGE 0
-#define VFD_CTRLREG1_REGID4INST 24
-#define VFD_CTRLREG1_REGID4VTX 16
-#define VFD_DECODEINSTRUCTIONS_CONSTFILL 4
-#define VFD_DECODEINSTRUCTIONS_FORMAT 6
-#define VFD_DECODEINSTRUCTIONS_LASTCOMPVALID 29
-#define VFD_DECODEINSTRUCTIONS_REGID 12
-#define VFD_DECODEINSTRUCTIONS_SHIFTCNT 24
-#define VFD_DECODEINSTRUCTIONS_SWITCHNEXT 30
-#define VFD_DECODEINSTRUCTIONS_WRITEMASK 0
-#define VFD_FETCHINSTRUCTIONS_BUFSTRIDE 7
-#define VFD_FETCHINSTRUCTIONS_FETCHSIZE 0
-#define VFD_FETCHINSTRUCTIONS_INDEXDECODE 18
-#define VFD_FETCHINSTRUCTIONS_STEPRATE 24
-#define VFD_FETCHINSTRUCTIONS_SWITCHNEXT 17
-#define VFD_THREADINGTHRESHOLD_REGID_VTXCNT 8
-#define VFD_THREADINGTHRESHOLD_REGID_THRESHOLD 0
-#define VFD_THREADINGTHRESHOLD_RESERVED6 4
-#define VPC_VPCATTR_LMSIZE 28
-#define VPC_VPCATTR_THRHDASSIGN 12
-#define VPC_VPCATTR_TOTALATTR 0
-#define VPC_VPCPACK_NUMFPNONPOSVAR 8
-#define VPC_VPCPACK_NUMNONPOSVSVAR 16
-#define VPC_VPCVARPSREPLMODE_COMPONENT08 0
-#define VPC_VPCVARPSREPLMODE_COMPONENT09 2
-#define VPC_VPCVARPSREPLMODE_COMPONENT0A 4
-#define VPC_VPCVARPSREPLMODE_COMPONENT0B 6
-#define VPC_VPCVARPSREPLMODE_COMPONENT0C 8
-#define VPC_VPCVARPSREPLMODE_COMPONENT0D 10
-#define VPC_VPCVARPSREPLMODE_COMPONENT0E 12
-#define VPC_VPCVARPSREPLMODE_COMPONENT0F 14
-#define VPC_VPCVARPSREPLMODE_COMPONENT10 16
-#define VPC_VPCVARPSREPLMODE_COMPONENT11 18
-#define VPC_VPCVARPSREPLMODE_COMPONENT12 20
-#define VPC_VPCVARPSREPLMODE_COMPONENT13 22
-#define VPC_VPCVARPSREPLMODE_COMPONENT14 24
-#define VPC_VPCVARPSREPLMODE_COMPONENT15 26
-#define VPC_VPCVARPSREPLMODE_COMPONENT16 28
-#define VPC_VPCVARPSREPLMODE_COMPONENT17 30
-
 /* RBBM Debug bus block IDs */
-#define RBBM_BLOCK_ID_NONE             0x0
 #define RBBM_BLOCK_ID_CP               0x1
 #define RBBM_BLOCK_ID_RBBM             0x2
 #define RBBM_BLOCK_ID_VBIF             0x3
@@ -871,7 +560,6 @@
 
 /* VBIF countables */
 #define VBIF_AXI_TOTAL_BEATS 85
-#define VBIF_DDR_TOTAL_CYCLES 110
 
 /* VBIF Recoverable HALT bit value */
 #define VBIF_RECOVERABLE_HALT_CTRL 0x1
diff --git a/drivers/gpu/msm/a4xx_reg.h b/drivers/gpu/msm/a4xx_reg.h
index 78db8dd2da40..4b69583a6ce1 100644
--- a/drivers/gpu/msm/a4xx_reg.h
+++ b/drivers/gpu/msm/a4xx_reg.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -102,7 +102,6 @@ enum a4xx_rb_perfctr_rb_sel {
 #define A4XX_RBBM_INTERFACE_HANG_INT_CTL	0x2f
 #define A4XX_RBBM_INT_CLEAR_CMD			0x36
 #define A4XX_RBBM_INT_0_MASK			0x37
-#define A4XX_RBBM_ALWAYSON_COUNTER_CNTL		0x3d
 #define A4XX_RBBM_RBBM_CTL			0x3e
 #define A4XX_RBBM_CLOCK_CTL2			0x42
 #define A4XX_RBBM_BLOCK_SW_RESET_CMD		0x45
@@ -113,13 +112,8 @@ enum a4xx_rb_perfctr_rb_sel {
 #define A4XX_RBBM_CFG_DEBBUS_SEL_D		0x4d
 #define A4XX_RBBM_CFG_DEBBUS_SEL_PING_INDEX_SHIFT	0
 #define A4XX_RBBM_CFG_DEBBUS_SEL_PING_BLK_SEL_SHIFT	8
-#define A4XX_RBBM_CFG_DEBBUS_SEL_PONG_INDEX_SHIFT	16
-#define A4XX_RBBM_CFG_DEBBUS_SEL_PONG_BLK_SEL_SHIFT	24
 
 #define A4XX_RBBM_CFG_DEBBUS_CTLT		0x4e
-#define A4XX_RBBM_CFG_DEBBUS_CTLT_ENT_SHIFT		0
-#define A4XX_RBBM_CFG_DEBBUS_CTLT_GRANU_SHIFT		12
-#define A4XX_RBBM_CFG_DEBBUS_CTLT_SEGT_SHIFT		28
 
 #define A4XX_RBBM_CFG_DEBBUS_CTLM		0x4f
 #define A4XX_RBBM_CFG_DEBBUS_CTLT_ENABLE_SHIFT		24
@@ -138,24 +132,7 @@ enum a4xx_rb_perfctr_rb_sel {
 
 
 #define A4XX_RBBM_CFG_DEBBUS_BYTEL_0		0x5a
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL0_SHIFT	0
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL1_SHIFT	4
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL2_SHIFT	8
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL3_SHIFT	12
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL4_SHIFT	16
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL5_SHIFT	20
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL6_SHIFT	24
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL7_SHIFT	28
-
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1			0x5b
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL8_SHIFT	0
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL9_SHIFT	4
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL10_SHIFT	8
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL11_SHIFT	12
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL12_SHIFT	16
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL13_SHIFT	20
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL14_SHIFT	24
-#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL15_SHIFT	28
+#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1		0x5b
 
 #define A4XX_RBBM_CFG_DEBBUS_IVTE_0		0x5c
 #define A4XX_RBBM_CFG_DEBBUS_IVTE_1		0x5d
@@ -425,14 +402,7 @@ enum a4xx_rb_perfctr_rb_sel {
 #define A4XX_RBBM_AHB_PFP_SPLIT_STATUS		0x18d
 #define A4XX_RBBM_AHB_ERROR_STATUS		0x18f
 #define A4XX_RBBM_STATUS			0x191
-#define A4XX_RBBM_CFG_COUNTER0			0x1a2
-#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF0		0x1a9
-#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF1		0x1aa
-#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF2		0x1ab
-#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF3		0x1ac
 #define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF4		0x1ad
-#define A4XX_RBBM_CFG_DEBBUS_MISR0		0x1ae
-#define A4XX_RBBM_CFG_DEBBUS_MISR1		0x1af
 #define A4XX_RBBM_POWER_STATUS			0x1b0
 #define A4XX_RBBM_PPD_V2_SP_PWR_WEIGHTS		0x1b2
 #define A4XX_RBBM_PPD_V2_SP_RB_EPOCH_TH		0x1b3
@@ -440,8 +410,6 @@ enum a4xx_rb_perfctr_rb_sel {
 #define A4XX_RBBM_PPD_RAMP_V2_CONTROL		0x1b5
 #define A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2		0x1b8
 #define A4XX_RBBM_PPD_CTRL			0x1b9
-#define A4XX_RBBM_PPD_EPOCH_INTRA_TH_1		0x1ba
-#define A4XX_RBBM_PPD_EPOCH_INTRA_TH_2		0x1bb
 #define A4XX_RBBM_PPD_EPOCH_INTER_TH_HIGH_CLEAR_THR  0x1bc
 #define A4XX_RBBM_PPD_EPOCH_INTER_TH_LOW	0x1bd
 /* SECVID registers */
@@ -473,13 +441,8 @@ enum a4xx_rb_perfctr_rb_sel {
 #define A4XX_CP_ME_RAM_WADDR		0x225
 #define A4XX_CP_ME_RAM_RADDR		0x226
 #define A4XX_CP_ME_RAM_DATA		0x227
-#define A4XX_CP_SCRATCH_UMASK		0x228
-#define A4XX_CP_SCRATCH_ADDR		0x229
 
 #define A4XX_CP_PREEMPT			0x22a
-/* PREEMPT register bit shifts */
-#define A4XX_CP_PREEMPT_STOP_SHIFT	0
-#define A4XX_CP_PREEMPT_RESUME_SHIFT	1
 
 #define A4XX_CP_PREEMPT_DISABLE		0x22b
 #define A4XX_CP_CNTL			0x22c
@@ -513,7 +476,6 @@ enum a4xx_rb_perfctr_rb_sel {
 #define A4XX_CP_PERFCTR_CP_SEL_6	0x506
 #define A4XX_CP_PERFCTR_CP_SEL_7	0x507
 
-#define A4XX_CP_SCRATCH_REG0		0x578
 #define A4XX_CP_SCRATCH_REG6		0x57e
 #define A4XX_CP_SCRATCH_REG7		0x57f
 #define A4XX_CP_SCRATCH_REG8		0x580
@@ -540,9 +502,6 @@ enum a4xx_rb_perfctr_rb_sel {
 #define A4XX_SP_CS_CTRL_0		0x2300
 #define A4XX_SP_CS_OBJ_OFFSET		0x2301
 #define A4XX_SP_CS_OBJ_START		0x2302
-#define A4XX_SP_CS_PVT_MEM_PARAM	0x2303
-#define A4XX_SP_CS_PVT_MEM_ADDR		0x2304
-#define A4XX_SP_CS_PVT_MEM_SIZE		0x2305
 #define A4XX_SP_CS_LENGTH		0x2306
 #define A4XX_SP_MODE_CONTROL		0xec3
 #define A4XX_SP_PERFCTR_SP_SEL_0	0xec4
@@ -611,8 +570,6 @@ enum a4xx_sp_perfctr_sp_sel {
 #define A4XX_VSC_PERFCTR_VSC_SEL_1	0xc51
 
 /* VFD registers */
-#define A4XX_VFD_CONTROL_0		0x2200
-#define A4XX_VFD_FETCH_INSTR_0_0	0x220a
 #define A4XX_VFD_FETCH_INSTR_1_31	0x2287
 #define A4XX_VFD_PERFCTR_VFD_SEL_0	0xe43
 #define A4XX_VFD_PERFCTR_VFD_SEL_1	0xe44
@@ -699,14 +656,6 @@ enum a4xx_vfd_perfctr_vfd_sel {
 
 #define A4XX_VBIF_TEST_BUS_OUT		0x308c
 
-#define A4XX_VBIF_PERF_CNT_EN0		0x30c0
-#define A4XX_VBIF_PERF_CNT_EN1		0x30c1
-#define A4XX_VBIF_PERF_CNT_EN2		0x30c2
-#define A4XX_VBIF_PERF_CNT_EN3		0x30c3
-#define A4XX_VBIF_PERF_CNT_CLR0		0x30c8
-#define A4XX_VBIF_PERF_CNT_CLR1		0x30c9
-#define A4XX_VBIF_PERF_CNT_CLR2		0x30ca
-#define A4XX_VBIF_PERF_CNT_CLR3		0x30cb
 #define A4XX_VBIF_PERF_CNT_SEL0		0x30d0
 #define A4XX_VBIF_PERF_CNT_SEL1		0x30d1
 #define A4XX_VBIF_PERF_CNT_SEL2		0x30d2
@@ -724,10 +673,6 @@ enum a4xx_vfd_perfctr_vfd_sel {
 #define A4XX_VBIF_PERF_PWR_CNT_EN1	0x3101
 #define A4XX_VBIF_PERF_PWR_CNT_EN2	0x3102
 #define A4XX_VBIF_PERF_PWR_CNT_EN3	0x3103
-#define A4XX_VBIF_PERF_PWR_CNT_CLR0	0x3108
-#define A4XX_VBIF_PERF_PWR_CNT_CLR1	0x3109
-#define A4XX_VBIF_PERF_PWR_CNT_CLR2	0x310A
-#define A4XX_VBIF_PERF_PWR_CNT_CLR3	0x310B
 #define A4XX_VBIF_PERF_PWR_CNT_LOW0	0x3110
 #define A4XX_VBIF_PERF_PWR_CNT_LOW1	0x3111
 #define A4XX_VBIF_PERF_PWR_CNT_LOW2	0x3112
@@ -737,12 +682,6 @@ enum a4xx_vfd_perfctr_vfd_sel {
 #define A4XX_VBIF_PERF_PWR_CNT_HIGH2	0x311a
 #define A4XX_VBIF_PERF_PWR_CNT_HIGH3	0x311b
 
-/* Bit flags for RBBM_CTL */
-#define A4XX_RBBM_RBBM_CTL_RESET_PWR_CTR0	0x00000001
-#define A4XX_RBBM_RBBM_CTL_RESET_PWR_CTR1	0x00000002
-#define A4XX_RBBM_RBBM_CTL_ENABLE_PWR_CTR0	0x00000010
-#define A4XX_RBBM_RBBM_CTL_ENABLE_PWR_CTR1	0x00000020
-
 /* GRAS registers */
 #define A4XX_GRAS_PERFCTR_TSE_SEL_0	0xc88
 #define A4XX_GRAS_PERFCTR_TSE_SEL_1	0xc89
@@ -772,7 +711,6 @@ enum a4xx_pc_perfctr_pc_sel {
 
 /* HLSQ registers */
 #define A4XX_HLSQ_TIMEOUT_THRESHOLD     0xe00
-#define A4XX_HLSQ_STATE_RESTORE_TRIGGER	0xe01
 #define A4XX_HLSQ_MODE_CONTROL		0xe05
 #define A4XX_HLSQ_PERFCTR_HLSQ_SEL_0	0xe06
 #define A4XX_HLSQ_PERFCTR_HLSQ_SEL_1	0xe07
@@ -784,24 +722,11 @@ enum a4xx_pc_perfctr_pc_sel {
 #define A4XX_HLSQ_PERFCTR_HLSQ_SEL_7	0xe0d
 #define A4XX_HLSQ_SPTP_RDSEL		0xe30
 #define A4xx_HLSQ_CONTROL_0		0x23c0
-#define A4xx_HLSQ_CONTROL_1		0x23c1
-#define A4xx_HLSQ_CONTROL_2		0x23c2
-#define A4xx_HLSQ_CONTROL_3		0x23c3
-#define A4xx_HLSQ_CONTROL_4		0x23c4
 #define A4XX_HLSQ_CS_CONTROL		0x23ca
 #define A4XX_HLSQ_CL_NDRANGE_0		0x23cd
-#define A4XX_HLSQ_CL_NDRANGE_1		0x23ce
-#define A4XX_HLSQ_CL_NDRANGE_2		0x23cf
-#define A4XX_HLSQ_CL_NDRANGE_3		0x23d0
-#define A4XX_HLSQ_CL_NDRANGE_4		0x23d1
-#define A4XX_HLSQ_CL_NDRANGE_5		0x23d2
-#define A4XX_HLSQ_CL_NDRANGE_6		0x23d3
 #define A4XX_HLSQ_CL_CONTROL_0		0x23d4
-#define A4XX_HLSQ_CL_CONTROL_1		0x23d5
 #define A4XX_HLSQ_CL_KERNEL_CONST	0x23d6
 #define A4XX_HLSQ_CL_KERNEL_GROUP_X	0x23d7
-#define A4XX_HLSQ_CL_KERNEL_GROUP_Y	0x23d8
-#define A4XX_HLSQ_CL_KERNEL_GROUP_Z	0x23d9
 #define A4XX_HLSQ_CL_WG_OFFSET		0x23da
 #define A4XX_HLSQ_UPDATE_CONTROL	0x23db
 
@@ -863,9 +788,6 @@ enum a4xx_uche_perfctr_uche_sel {
 #define A4XX_TPL1_PERFCTR_TP_SEL_6	0xf0a
 #define A4XX_TPL1_PERFCTR_TP_SEL_7	0xf0b
 #define A4XX_TPL1_TP_TEX_TSIZE_1	0x23a0
-#define A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR	0x23A4
-#define A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR	0x23A5
-#define A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR	0x23A6
 
 enum a4xx_tpl1_perfctr_tp_sel {
 	TP_OUTPUT_TEXELS_POINT = 0x2,
diff --git a/drivers/gpu/msm/a5xx_reg.h b/drivers/gpu/msm/a5xx_reg.h
index ccb5d834dc2a..372bfad48a09 100644
--- a/drivers/gpu/msm/a5xx_reg.h
+++ b/drivers/gpu/msm/a5xx_reg.h
@@ -131,9 +131,6 @@
 #define A5XX_CP_POWERCTR_CP_SEL_2        0xBBC
 #define A5XX_CP_POWERCTR_CP_SEL_3        0xBBD
 
-/* CP_EVENT_WRITE events */
-#define A5XX_CACHE_FLUSH_TS              0x4
-
 /* RBBM registers */
 #define A5XX_RBBM_CFG_DBGBUS_SEL_A               0x4
 #define A5XX_RBBM_CFG_DBGBUS_SEL_B               0x5
@@ -141,8 +138,6 @@
 #define A5XX_RBBM_CFG_DBGBUS_SEL_D               0x7
 #define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT    0x0
 #define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT  0x8
-#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT    0x10
-#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT  0x18
 
 #define A5XX_RBBM_CFG_DBGBUS_CNTLT               0x8
 #define A5XX_RBBM_CFG_DBGBUS_CNTLM               0x9
@@ -536,10 +531,6 @@
 #define A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI     0xF801
 #define A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE        0xF802
 #define A5XX_RBBM_SECVID_TSB_CNTL                0xF803
-#define A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO      0xF804
-#define A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI      0xF805
-#define A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO      0xF806
-#define A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI      0xF807
 #define A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL      0xF810
 
 /* VSC registers */
@@ -614,7 +605,6 @@
 #define A5XX_PC_PERFCTR_PC_SEL_7            0xD17
 
 /* HLSQ registers */
-#define A5XX_HLSQ_TIMEOUT_THRESHOLD         0xE00
 #define A5XX_HLSQ_ADDR_MODE_CNTL            0xE05
 #define A5XX_HLSQ_PERFCTR_HLSQ_SEL_0        0xE10
 #define A5XX_HLSQ_PERFCTR_HLSQ_SEL_1        0xE11
@@ -624,7 +614,6 @@
 #define A5XX_HLSQ_PERFCTR_HLSQ_SEL_5        0xE15
 #define A5XX_HLSQ_PERFCTR_HLSQ_SEL_6        0xE16
 #define A5XX_HLSQ_PERFCTR_HLSQ_SEL_7        0xE17
-#define A5XX_HLSQ_SPTP_RDSEL                0xF08
 #define A5XX_HLSQ_DBG_READ_SEL              0xBC00
 #define A5XX_HLSQ_DBG_AHB_READ_APERTURE     0xA000
 
@@ -648,7 +637,6 @@
 
 /* UCHE registers */
 #define A5XX_UCHE_ADDR_MODE_CNTL            0xE80
-#define A5XX_UCHE_SVM_CNTL                  0xE82
 #define A5XX_UCHE_WRITE_THRU_BASE_LO        0xE87
 #define A5XX_UCHE_WRITE_THRU_BASE_HI        0xE88
 #define A5XX_UCHE_TRAP_BASE_LO              0xE89
@@ -721,12 +709,8 @@
 #define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK   0x1
 #define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT  0x1
 
-#define A5XX_VBIF_ABIT_SORT                0x3028
-#define A5XX_VBIF_ABIT_SORT_CONF           0x3029
 #define A5XX_VBIF_ROUND_ROBIN_QOS_ARB      0x3049
 #define A5XX_VBIF_GATE_OFF_WRREQ_EN        0x302A
-#define A5XX_VBIF_IN_RD_LIM_CONF0          0x302C
-#define A5XX_VBIF_IN_RD_LIM_CONF1          0x302D
 
 #define A5XX_VBIF_XIN_HALT_CTRL0	   0x3080
 #define A5XX_VBIF_XIN_HALT_CTRL0_MASK	   0xF
@@ -877,9 +861,7 @@
 
 #define A5XX_GPMU_TEMP_SENSOR_ID		0xAC00
 #define A5XX_GPMU_TEMP_SENSOR_CONFIG		0xAC01
-#define A5XX_GPMU_TEMP_VAL			0xAC02
 #define A5XX_GPMU_DELTA_TEMP_THRESHOLD		0xAC03
-#define A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS	0xAC05
 #define A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK	0xAC06
 
 #define A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1	0xAC40
@@ -897,7 +879,6 @@
 #define A5XX_GPMU_GPMU_ISENSE_CTRL		0xACD0
 
 #define A5XX_GDPM_CONFIG1			0xB80C
-#define A5XX_GDPM_CONFIG2			0xB80D
 #define A5XX_GDPM_INT_EN			0xB80F
 #define A5XX_GDPM_INT_MASK			0xB811
 #define A5XX_GPMU_BEC_ENABLE			0xB9A0
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 816185e9aad4..875b186cde3f 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -55,9 +55,6 @@
 /* ADRENO_GPUREV - Return the GPU ID for the given adreno_device */
 #define ADRENO_GPUREV(_a) ((_a)->gpucore->gpurev)
 
-/* ADRENO_GPUREV - Return the GPU patchid for the given adreno_device */
-#define ADRENO_PATCHID(_a) ((_a)->gpucore->patchid)
-
 /*
  * ADRENO_FEATURE - return true if the specified feature is supported by the GPU
  * core
@@ -132,7 +129,6 @@
 #define KGSL_CMD_FLAGS_WFI              BIT(2)
 #define KGSL_CMD_FLAGS_PROFILE		BIT(3)
 #define KGSL_CMD_FLAGS_PWRON_FIXUP      BIT(4)
-#define KGSL_CMD_FLAGS_MEMLIST          BIT(5)
 
 /* Command identifiers */
 #define KGSL_CONTEXT_TO_MEM_IDENTIFIER	0x2EADBEEF
@@ -140,16 +136,10 @@
 #define KGSL_CMD_INTERNAL_IDENTIFIER	0x2EEDD00D
 #define KGSL_START_OF_IB_IDENTIFIER	0x2EADEABE
 #define KGSL_END_OF_IB_IDENTIFIER	0x2ABEDEAD
-#define KGSL_END_OF_FRAME_IDENTIFIER	0x2E0F2E0F
-#define KGSL_NOP_IB_IDENTIFIER	        0x20F20F20
 #define KGSL_START_OF_PROFILE_IDENTIFIER	0x2DEFADE1
 #define KGSL_END_OF_PROFILE_IDENTIFIER	0x2DEFADE2
 #define KGSL_PWRON_FIXUP_IDENTIFIER	0x2AFAFAFA
 
-#define ADRENO_ISTORE_START 0x5000 /* Istore offset */
-
-#define ADRENO_NUM_CTX_SWITCH_ALLOWED_BEFORE_DRAW	50
-
 /* One cannot wait forever for the core to idle, so set an upper limit to the
  * amount of time to wait for the core to go idle
  */
@@ -734,11 +724,6 @@ struct adreno_gpudev {
 	void (*pre_reset)(struct adreno_device *);
 };
 
-struct log_field {
-	bool show;
-	const char *display;
-};
-
 /**
  * enum kgsl_ft_policy_bits - KGSL fault tolerance policy bits
  * @KGSL_FT_OFF: Disable fault detection (not used)
diff --git a/drivers/gpu/msm/adreno_a5xx.h b/drivers/gpu/msm/adreno_a5xx.h
index c627aa3d2d98..67b2d6f0d02c 100644
--- a/drivers/gpu/msm/adreno_a5xx.h
+++ b/drivers/gpu/msm/adreno_a5xx.h
@@ -97,6 +97,7 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 /* A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL */
 #define STATE_OF_CHILD			GENMASK(5, 4)
 #define STATE_OF_CHILD_01		BIT(4)
+#define STATE_OF_CHILD_11		(BIT(4) | BIT(5))
 #define IDLE_FULL_LM_SLEEP		BIT(0)
 
 /* A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS */
@@ -109,7 +110,6 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 /* A5XX_GPMU_TEMP_SENSOR_CONFIG */
 #define GPMU_BCL_ENABLED		BIT(4)
 #define GPMU_LLM_ENABLED		BIT(9)
-#define GPMU_LMH_ENABLED		BIT(8)
 #define GPMU_ISENSE_STATUS		GENMASK(3, 0)
 #define GPMU_ISENSE_END_POINT_CAL_ERR	BIT(0)
 
@@ -122,7 +122,6 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 
 /* A5XX_GPU_CS_AMP_CALIBRATION_STATUS*_* */
 #define AMP_OUT_OF_RANGE_ERR		BIT(4)
-#define AMP_CHECK_TIMEOUT_ERR		BIT(3)
 #define AMP_OFFSET_CHECK_MAX_ERR	BIT(2)
 #define AMP_OFFSET_CHECK_MIN_ERR	BIT(1)
 
@@ -142,20 +141,12 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 #define PWR_THRESHOLD_VALID		0x80000000
 /* AGC */
 #define AGC_INIT_BASE			A5XX_GPMU_DATA_RAM_BASE
-#define AGC_RVOUS_MAGIC			(AGC_INIT_BASE + 0)
-#define AGC_KMD_GPMU_ADDR		(AGC_INIT_BASE + 1)
-#define AGC_KMD_GPMU_BYTES		(AGC_INIT_BASE + 2)
-#define AGC_GPMU_KMD_ADDR		(AGC_INIT_BASE + 3)
-#define AGC_GPMU_KMD_BYTES		(AGC_INIT_BASE + 4)
 #define AGC_INIT_MSG_MAGIC		(AGC_INIT_BASE + 5)
-#define AGC_RESERVED			(AGC_INIT_BASE + 6)
 #define AGC_MSG_BASE			(AGC_INIT_BASE + 7)
 
 #define AGC_MSG_STATE			(AGC_MSG_BASE + 0)
 #define AGC_MSG_COMMAND			(AGC_MSG_BASE + 1)
-#define AGC_MSG_RETURN			(AGC_MSG_BASE + 2)
 #define AGC_MSG_PAYLOAD_SIZE		(AGC_MSG_BASE + 3)
-#define AGC_MSG_MAX_RETURN_SIZE		(AGC_MSG_BASE + 4)
 #define AGC_MSG_PAYLOAD			(AGC_MSG_BASE + 5)
 
 #define AGC_INIT_MSG_VALUE		0xBABEFACE
@@ -163,14 +154,9 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 
 #define AGC_LM_CONFIG			(136/4)
 #define AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE (1)
-#define AGC_LM_CONFIG_ENABLE_GPMU_LEGACY   (2)
-#define AGC_LM_CONFIG_ENABLE_GPMU_LLM	(3)
 
-#define AGC_LM_CONFIG_ENABLE_ISENSE	(1 << 4)
-#define AGC_LM_CONFIG_ENABLE_DPM	(2 << 4)
 #define AGC_LM_CONFIG_ENABLE_ERROR	(3 << 4)
 
-#define AGC_THROTTLE_SEL_CRC		(0 << 8)
 #define AGC_THROTTLE_SEL_DCS		(1 << 8)
 
 #define AGC_LLM_ENABLED			(1 << 16)
@@ -180,12 +166,9 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 
 
 #define AGC_LEVEL_CONFIG		(140/4)
-#define AGC_LEVEL_CONFIG_SENSOR_DISABLE	GENMASK(15, 0)
-#define AGC_LEVEL_CONFIG_LMDISABLE	GENMASK(31, 16)
 
 #define LM_DCVS_LIMIT			2
 /* FW file tages */
-#define GPMU_HEADER_ID			1
 #define GPMU_FIRMWARE_ID		2
 #define GPMU_SEQUENCE_ID		3
 #define GPMU_INST_RAM_SIZE		0xFFF
@@ -199,7 +182,6 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 #define MAX_HEADER_SIZE			10
 
 #define LM_SEQUENCE_ID			1
-#define HWCG_SEQUENCE_ID		2
 #define MAX_SEQUENCE_ID			3
 
 /* LM defaults */
diff --git a/drivers/gpu/msm/adreno_drawctxt.c b/drivers/gpu/msm/adreno_drawctxt.c
index cef4bb4db3a0..d8498d938b6a 100644
--- a/drivers/gpu/msm/adreno_drawctxt.c
+++ b/drivers/gpu/msm/adreno_drawctxt.c
@@ -21,8 +21,6 @@
 #include "adreno.h"
 #include "adreno_trace.h"
 
-#define KGSL_INIT_REFTIMESTAMP		0x7FFFFFFF
-
 static void wait_callback(struct kgsl_device *device,
 		struct kgsl_event_group *group, void *priv, int result)
 {
diff --git a/drivers/gpu/msm/adreno_drawctxt.h b/drivers/gpu/msm/adreno_drawctxt.h
index 09683b1bb2ba..7e80247e9322 100644
--- a/drivers/gpu/msm/adreno_drawctxt.h
+++ b/drivers/gpu/msm/adreno_drawctxt.h
@@ -83,9 +83,6 @@ struct adreno_context {
 
 /* Flag definitions for flag field in adreno_context */
 
-/* Set when sync timer of cmdbatch belonging to the context times out */
-#define ADRENO_CONTEXT_CMDBATCH_FLAG_FENCE_LOG	BIT(0)
-
 /**
  * enum adreno_context_priv - Private flags for an adreno draw context
  * @ADRENO_CONTEXT_FAULT - set if the context has faulted (and recovered)
diff --git a/drivers/gpu/msm/adreno_perfcounter.c b/drivers/gpu/msm/adreno_perfcounter.c
index 1779e8e7c0b7..96922972200f 100644
--- a/drivers/gpu/msm/adreno_perfcounter.c
+++ b/drivers/gpu/msm/adreno_perfcounter.c
@@ -27,13 +27,9 @@
 #define VBIF2_PERF_CLR_REG_SEL_OFF 8
 /* offset of enable register from select register */
 #define VBIF2_PERF_EN_REG_SEL_OFF 16
-/* offset of high counter from low counter value */
-#define VBIF2_PERF_HIGH_REG_LOW_OFF 8
 
 /* offset of clear register from the enable register */
 #define VBIF2_PERF_PWR_CLR_REG_EN_OFF 8
-/* offset of high counter from low counter value */
-#define VBIF2_PERF_PWR_HIGH_REG_LOW_OFF 8
 
 #define REG_64BIT_VAL(hi, lo, val) (((((uint64_t) hi) << 32) | lo) + val)
 /*
diff --git a/drivers/gpu/msm/adreno_pm4types.h b/drivers/gpu/msm/adreno_pm4types.h
index f81c0f20e10b..ec2c29b929c1 100644
--- a/drivers/gpu/msm/adreno_pm4types.h
+++ b/drivers/gpu/msm/adreno_pm4types.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002,2007-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2002,2007-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -15,8 +15,6 @@
 
 #include "adreno.h"
 
-#define CP_PKT_MASK	0xc0000000
-
 #define CP_TYPE0_PKT	((unsigned int)0 << 30)
 #define CP_TYPE3_PKT	((unsigned int)3 << 30)
 #define CP_TYPE4_PKT    ((unsigned int)4 << 28)
@@ -32,21 +30,10 @@
 #define CP_PREEMPT_TOKEN 0x1E
 /* Bit to set in CP_PREEMPT_TOKEN ordinal for interrupt on preemption */
 #define CP_PREEMPT_ORDINAL_INTERRUPT 24
-/* copy from ME scratch RAM to a register */
-#define CP_SCRATCH_TO_REG      0x4d
-
-/* Copy from REG to ME scratch RAM */
-#define CP_REG_TO_SCRATCH      0x4a
 
 /* Wait for memory writes to complete */
 #define CP_WAIT_MEM_WRITES     0x12
 
-/* Conditional execution based on register comparison */
-#define CP_COND_REG_EXEC       0x47
-
-/* Memory to REG copy */
-#define CP_MEM_TO_REG          0x42
-
 /* initialize CP's micro-engine */
 #define CP_ME_INIT		0x48
 
@@ -68,12 +55,6 @@
 /* switches SMMU pagetable, used on a5xx only */
 #define CP_SMMU_TABLE_UPDATE 0x53
 
-/* wait until a read completes */
-#define CP_WAIT_UNTIL_READ	0x5c
-
-/* wait until all base/size writes from an IB_PFD packet have completed */
-#define CP_WAIT_IB_PFD_COMPLETE 0x5d
-
 /* register read/modify/write */
 #define CP_REG_RMW		0x21
 
@@ -86,9 +67,6 @@
 /* write N 32-bit words to memory */
 #define CP_MEM_WRITE		0x3d
 
-/* write CP_PROG_COUNTER value to memory */
-#define CP_MEM_WRITE_CNTR	0x4f
-
 /* conditional execution of a sequence of packets */
 #define CP_COND_EXEC		0x44
 
@@ -98,69 +76,21 @@
 /* generate an event that creates a write to memory when completed */
 #define CP_EVENT_WRITE		0x46
 
-/* generate a VS|PS_done event */
-#define CP_EVENT_WRITE_SHD	0x58
-
-/* generate a cache flush done event */
-#define CP_EVENT_WRITE_CFL	0x59
-
-/* generate a z_pass done event */
-#define CP_EVENT_WRITE_ZPD	0x5b
-
-
 /* initiate fetch of index buffer and draw */
 #define CP_DRAW_INDX		0x22
 
-/* draw using supplied indices in packet */
-#define CP_DRAW_INDX_2		0x36
-
-/* initiate fetch of index buffer and binIDs and draw */
-#define CP_DRAW_INDX_BIN	0x34
-
-/* initiate fetch of bin IDs and draw using supplied indices */
-#define CP_DRAW_INDX_2_BIN	0x35
-
 /* New draw packets defined for A4XX */
 #define CP_DRAW_INDX_OFFSET	0x38
 #define CP_DRAW_INDIRECT	0x28
 #define CP_DRAW_INDX_INDIRECT	0x29
 #define CP_DRAW_AUTO		0x24
 
-/* begin/end initiator for viz query extent processing */
-#define CP_VIZ_QUERY		0x23
-
-/* fetch state sub-blocks and initiate shader code DMAs */
-#define CP_SET_STATE		0x25
-
 /* load constant into chip and to memory */
 #define CP_SET_CONSTANT	0x2d
 
-/* load sequencer instruction memory (pointer-based) */
-#define CP_IM_LOAD		0x27
-
-/* load sequencer instruction memory (code embedded in packet) */
-#define CP_IM_LOAD_IMMEDIATE	0x2b
-
-/* load constants from a location in memory */
-#define CP_LOAD_CONSTANT_CONTEXT 0x2e
-
 /* selective invalidation of state pointers */
 #define CP_INVALIDATE_STATE	0x3b
 
-
-/* dynamically changes shader instruction memory partition */
-#define CP_SET_SHADER_BASES	0x4A
-
-/* sets the 64-bit BIN_MASK register in the PFP */
-#define CP_SET_BIN_MASK	0x50
-
-/* sets the 64-bit BIN_SELECT register in the PFP */
-#define CP_SET_BIN_SELECT	0x51
-
-
-/* updates the current context, if needed */
-#define CP_CONTEXT_UPDATE	0x5e
-
 /* generate interrupt from the command stream */
 #define CP_INTERRUPT		0x40
 
@@ -179,12 +109,6 @@
 /* Inform CP about current render mode (needed for a5xx preemption) */
 #define CP_SET_RENDER_MODE          0x6C
 
-/* copy sequencer instruction memory to system memory */
-#define CP_IM_STORE            0x2c
-
-/* test 2 memory locations to dword values specified */
-#define CP_TEST_TWO_MEMS	0x71
-
 /* Write register, ignoring context state for context sensitive registers */
 #define CP_REG_WR_NO_CTXT  0x78
 
@@ -198,9 +122,6 @@
 /* PFP waits until the FIFO between the PFP and the ME is empty */
 #define CP_WAIT_FOR_ME		0x13
 
-/* Record the real-time when this packet is processed by PFP */
-#define CP_RECORD_PFP_TIMESTAMP	0x11
-
 #define CP_SET_PROTECTED_MODE  0x5f /* sets the register protection mode */
 
 /* Used to switch GPU between secure and non-secure modes */
diff --git a/drivers/gpu/msm/adreno_ringbuffer.h b/drivers/gpu/msm/adreno_ringbuffer.h
index e433a2f275e2..f1980fd92961 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.h
+++ b/drivers/gpu/msm/adreno_ringbuffer.h
@@ -105,7 +105,6 @@ struct adreno_ringbuffer_pagetable_info {
 struct adreno_ringbuffer {
 	uint32_t flags;
 	struct kgsl_memdesc buffer_desc;
-	unsigned int sizedwords;
 	unsigned int wptr;
 	unsigned int rptr;
 	unsigned int last_wptr;
@@ -125,16 +124,6 @@ struct adreno_ringbuffer {
 	enum adreno_dispatcher_starve_timer_states starve_timer_state;
 };
 
-/* enable timestamp (...scratch0) memory shadowing */
-#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x1
-
-/*
- * protected mode error checking below register address 0x800
- * note: if CP_INTERRUPT packet is used then checking needs
- * to change to below register address 0x7C8
- */
-#define GSL_RB_PROTECTED_MODE_CONTROL		0x200001F2
-
 /* Returns the current ringbuffer */
 #define ADRENO_CURRENT_RINGBUFFER(a)	((a)->cur_rb)
 
diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c
index f9834b973a4e..6c91eb3a3dc9 100644
--- a/drivers/gpu/msm/adreno_snapshot.c
+++ b/drivers/gpu/msm/adreno_snapshot.c
@@ -21,9 +21,6 @@
 #include "adreno_snapshot.h"
 #include "adreno_a5xx.h"
 
-/* Number of dwords of ringbuffer history to record */
-#define NUM_DWORDS_OF_RINGBUFFER_HISTORY 100
-
 #define VPC_MEMORY_BANKS 4
 
 /* Maintain a list of the objects we see during parsing */
diff --git a/drivers/gpu/msm/kgsl_cffdump.c b/drivers/gpu/msm/kgsl_cffdump.c
index 1f10a333adf7..2e90f78a303c 100644
--- a/drivers/gpu/msm/kgsl_cffdump.c
+++ b/drivers/gpu/msm/kgsl_cffdump.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -72,8 +72,6 @@ struct cff_op_wait_irq {
 	unsigned char op;
 } __packed;
 
-#define CFF_OP_RMW              0x0000000a
-
 struct cff_op_write_mem {
 	unsigned char op;
 	uint addr;
diff --git a/drivers/gpu/msm/kgsl_compat.h b/drivers/gpu/msm/kgsl_compat.h
index b7a1eb174baf..ca1685e5fcf5 100644
--- a/drivers/gpu/msm/kgsl_compat.h
+++ b/drivers/gpu/msm/kgsl_compat.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -92,16 +92,6 @@ struct kgsl_ringbuffer_issueibcmds_compat {
 #define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS_COMPAT \
 	_IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds_compat)
 
-struct kgsl_cmdstream_freememontimestamp_compat {
-	compat_ulong_t gpuaddr;
-	unsigned int type;
-	unsigned int timestamp;
-};
-
-#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_COMPAT \
-	_IOW(KGSL_IOC_TYPE, 0x12, \
-	struct kgsl_cmdstream_freememontimestamp_compat)
-
 struct kgsl_cmdstream_freememontimestamp_ctxtid_compat {
 	unsigned int context_id;
 	compat_ulong_t gpuaddr;
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index b0540a3830ee..c3fb2b81fcbd 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -27,10 +27,6 @@
 #include "kgsl_sharedmem.h"
 #include "kgsl_cmdbatch.h"
 
-#define KGSL_TIMEOUT_NONE           0
-#define KGSL_TIMEOUT_DEFAULT        0xFFFFFFFF
-#define KGSL_TIMEOUT_PART           50 /* 50 msec */
-
 #define KGSL_IOCTL_FUNC(_cmd, _func) \
 	[_IOC_NR((_cmd))] = \
 		{ .cmd = (_cmd), .func = (_func) }
@@ -53,10 +49,6 @@
 #define KGSL_STATE_SLUMBER	0x00000080
 #define KGSL_STATE_DEEP_NAP	0x00000100
 
-#define KGSL_GRAPHICS_MEMORY_LOW_WATERMARK  0x1000000
-
-#define KGSL_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK)))
-
 /**
  * enum kgsl_event_results - result codes passed to an event callback when the
  * event is retired or cancelled
@@ -342,14 +334,10 @@ struct kgsl_process_private;
  * @priv: in-kernel context flags, use KGSL_CONTEXT_* values
  * @reset_status: status indication whether a gpu reset occured and whether
  * this context was responsible for causing it
- * @wait_on_invalid_ts: flag indicating if this context has tried to wait on a
- * bad timestamp
  * @timeline: sync timeline used to create fences that can be signaled when a
  * sync_pt timestamp expires
  * @events: A kgsl_event_group for this context - contains the list of GPU
  * events
- * @pagefault_ts: global timestamp of the pagefault, if KGSL_CONTEXT_PAGEFAULT
- * is set.
  * @flags: flags from userspace controlling the behavior of this context
  * @pwr_constraint: power constraint from userspace for this context
  * @fault_count: number of times gpu hanged in last _context_throttle_time ms
@@ -365,10 +353,8 @@ struct kgsl_context {
 	unsigned long priv;
 	struct kgsl_device *device;
 	unsigned int reset_status;
-	bool wait_on_invalid_ts;
 	struct sync_timeline *timeline;
 	struct kgsl_event_group events;
-	unsigned int pagefault_ts;
 	unsigned int flags;
 	struct kgsl_pwr_constraint pwr_constraint;
 	unsigned int fault_count;
diff --git a/drivers/gpu/msm/kgsl_iommu.h b/drivers/gpu/msm/kgsl_iommu.h
index f82452dd6080..06f6d65effad 100644
--- a/drivers/gpu/msm/kgsl_iommu.h
+++ b/drivers/gpu/msm/kgsl_iommu.h
@@ -45,20 +45,6 @@
 #define KGSL_IOMMU_SVM_BASE64		0x700000000ULL
 #define KGSL_IOMMU_SVM_END64		0x800000000ULL
 
-/* Pagetable virtual base */
-#define KGSL_IOMMU_CTX_OFFSET_V1	0x8000
-#define KGSL_IOMMU_CTX_OFFSET_V2	0x9000
-#define KGSL_IOMMU_CTX_OFFSET_V2_A530	0x8000
-#define KGSL_IOMMU_CTX_OFFSET_A405V2	0x8000
-#define KGSL_IOMMU_CTX_SHIFT		12
-
-/* FSYNR1 V0 fields */
-#define KGSL_IOMMU_FSYNR1_AWRITE_MASK		0x00000001
-#define KGSL_IOMMU_FSYNR1_AWRITE_SHIFT		8
-/* FSYNR0 V1 fields */
-#define KGSL_IOMMU_V1_FSYNR0_WNR_MASK		0x00000001
-#define KGSL_IOMMU_V1_FSYNR0_WNR_SHIFT		4
-
 /* TLBSTATUS register fields */
 #define KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE BIT(0)
 
diff --git a/drivers/gpu/msm/kgsl_log.h b/drivers/gpu/msm/kgsl_log.h
index 70480f8e9189..51baabefb6d3 100644
--- a/drivers/gpu/msm/kgsl_log.h
+++ b/drivers/gpu/msm/kgsl_log.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002,2008-2011,2013-2014 The Linux Foundation.
+/* Copyright (c) 2002,2008-2011,2013-2014,2016 The Linux Foundation.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -48,9 +48,6 @@
 		BUG(); \
 	} while (0)
 
-#define KGSL_LOG_POSTMORTEM_WRITE(_dev, fmt, args...) \
-	do { dev_crit(_dev->dev, fmt, ##args); } while (0)
-
 #define KGSL_LOG_DUMP(_dev, fmt, args...)	dev_err(_dev->dev, fmt, ##args)
 
 #define KGSL_DEV_ERR_ONCE(_dev, fmt, args...) \
@@ -83,24 +80,6 @@ KGSL_LOG_CRIT_RATELIMITED(_dev->dev, _dev->drv_log, fmt, ##args)
 #define KGSL_DRV_FATAL(_dev, fmt, args...) \
 KGSL_LOG_FATAL((_dev)->dev, (_dev)->drv_log, fmt, ##args)
 
-#define KGSL_CMD_INFO(_dev, fmt, args...) \
-KGSL_LOG_INFO(_dev->dev, _dev->cmd_log, fmt, ##args)
-#define KGSL_CMD_WARN(_dev, fmt, args...) \
-KGSL_LOG_WARN(_dev->dev, _dev->cmd_log, fmt, ##args)
-#define KGSL_CMD_ERR(_dev, fmt, args...) \
-KGSL_LOG_ERR(_dev->dev, _dev->cmd_log, fmt, ##args)
-#define KGSL_CMD_CRIT(_dev, fmt, args...) \
-KGSL_LOG_CRIT(_dev->dev, _dev->cmd_log, fmt, ##args)
-
-#define KGSL_CTXT_INFO(_dev, fmt, args...) \
-KGSL_LOG_INFO(_dev->dev, _dev->ctxt_log, fmt, ##args)
-#define KGSL_CTXT_WARN(_dev, fmt, args...) \
-KGSL_LOG_WARN(_dev->dev, _dev->ctxt_log, fmt, ##args)
-#define KGSL_CTXT_ERR(_dev, fmt, args...)  \
-KGSL_LOG_ERR(_dev->dev, _dev->ctxt_log, fmt, ##args)
-#define KGSL_CTXT_CRIT(_dev, fmt, args...) \
-KGSL_LOG_CRIT(_dev->dev, _dev->ctxt_log, fmt, ##args)
-
 #define KGSL_MEM_INFO(_dev, fmt, args...) \
 KGSL_LOG_INFO(_dev->dev, _dev->mem_log, fmt, ##args)
 #define KGSL_MEM_WARN(_dev, fmt, args...) \
@@ -125,13 +104,4 @@ KGSL_LOG_CRIT(_dev->dev, _dev->pwr_log, fmt, ##args)
 #define KGSL_CORE_ERR(fmt, args...) \
 pr_err("kgsl: %s: " fmt, __func__, ##args)
 
-#define KGSL_CORE_ERR_ONCE(fmt, args...) \
-({ \
-	static bool kgsl_core_err_once; \
-	if (!kgsl_core_err_once) { \
-		kgsl_core_err_once = true; \
-		pr_err("kgsl: %s: " fmt, __func__, ##args); \
-	} \
-})
-
 #endif /* __KGSL_LOG_H */
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index f9b5545519cb..927841a7ad3b 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -35,23 +35,12 @@
 
 #define UPDATE_BUSY_VAL		1000000
 
-/*
- * Expected delay for post-interrupt processing on A3xx.
- * The delay may be longer, gradually increase the delay
- * to compensate.  If the GPU isn't done by max delay,
- * it's working on something other than just the final
- * command sequence so stop waiting for it to be idle.
- */
-#define INIT_UDELAY		200
-#define MAX_UDELAY		2000
-
 /* Number of jiffies for a full thermal cycle */
 #define TH_HZ			(HZ/5)
 
 #define KGSL_MAX_BUSLEVELS	20
 
 #define DEFAULT_BUS_P 25
-#define DEFAULT_BUS_DIV (100 / DEFAULT_BUS_P)
 
 /*
  * The effective duration of qos request in usecs. After
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index 7ed76760c043..9fcea11c805b 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -22,8 +22,6 @@
 #define KGSL_PWRFLAGS_OFF  0
 
 #define KGSL_PWRLEVEL_TURBO 0
-#define KGSL_PWRLEVEL_NOMINAL 1
-#define KGSL_PWRLEVEL_LAST_OFFSET 2
 
 #define KGSL_PWR_ON	0xFFFF
 
diff --git a/drivers/gpu/msm/kgsl_pwrscale.c b/drivers/gpu/msm/kgsl_pwrscale.c
index 4ee1816a66f0..4f6677d9a1de 100644
--- a/drivers/gpu/msm/kgsl_pwrscale.c
+++ b/drivers/gpu/msm/kgsl_pwrscale.c
@@ -19,9 +19,6 @@
 #include "kgsl_device.h"
 #include "kgsl_trace.h"
 
-#define FAST_BUS 1
-#define SLOW_BUS -1
-
 /*
  * "SLEEP" is generic counting both NAP & SLUMBER
  * PERIODS generally won't exceed 9 for the relavent 150msec