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authorTrilok Soni <tsoni@codeaurora.org>2015-12-08 17:15:18 -0800
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-22 11:08:51 -0700
commit7ae4a36f579ab6deaf17036558b6b33fc76fa04b (patch)
tree43abe347cbf77954642108bcc1f0edaf6cdbce08
parenta1c9d666be3e2c85c914b82cd1a201a3fd2be42d (diff)
irqchip: gicv3: Add GICv3 access control Kconfig option
Some SOCs(System-on-chip) S/W configurations restricts the access to particular set of the GIC registers to prevent invalid accesses for the security reasons. Provide a configuration option for the GICv3 driver and also restrict the access of the GICR_WAKER registers from the non-secure world. If this Kconfig option is not selected then it means that access control configuration is enabled from the secure world. CRs-Fixed: 958251 Change-Id: I91f06484b6b6bf58d05e6b621ee84610a71fe3e7 [abhimany: minor merge conflict resolution] Signed-off-by: Trilok Soni <tsoni@codeaurora.org> Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
-rw-r--r--drivers/irqchip/Kconfig12
-rw-r--r--drivers/irqchip/irq-gic-v3.c4
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 463dbf3dbf6d..ef3e3c9725ee 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -27,6 +27,18 @@ config ARM_GIC_V3_ITS
bool
select PCI_MSI_IRQ_DOMAIN
+config ARM_GIC_V3_NO_ACCESS_CONTROL
+ bool "GICv3 No Access Control Configuration"
+ depends on ARM_GIC_V3
+ help
+ On some SOCs with the access control configurations it is
+ not allowed to access certain set of the GIC registers
+ from non-secure world. Provide a common flag to protect
+ those functionalities and compile them out for such
+ configurations, so that specific registers are not touched.
+
+ For production kernels, you should say 'N' here.
+
config ARM_NVIC
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 1a1d7ce9c90f..6bcf4281422c 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -126,6 +126,7 @@ static u64 __maybe_unused gic_read_iar(void)
}
#endif
+#ifdef CONFIG_ARM_GIC_V3_NO_ACCESS_CONTROL
static void gic_enable_redist(bool enable)
{
void __iomem *rbase;
@@ -159,6 +160,9 @@ static void gic_enable_redist(bool enable)
pr_err_ratelimited("redistributor failed to %s...\n",
enable ? "wakeup" : "sleep");
}
+#else
+static void gic_enable_redist(bool enable) { }
+#endif
/*
* Routines to disable, enable, EOI and route interrupts