diff options
| author | Mike Dyer <mike.dyer@md-soft.co.uk> | 2013-08-16 18:36:28 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2013-08-18 16:30:26 +0100 |
| commit | 85fa532b6ef920b32598df86b194571a7059a77c (patch) | |
| tree | a8e6b1f126b056005af744fc5d408458ed472f62 | |
| parent | d4e4ab86bcba5a72779c43dc1459f71fea3d89c8 (diff) | |
ASoC: wm8960: Fix PLL register writes
Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.
Signed-off-by: Mike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
| -rw-r--r-- | sound/soc/codecs/wm8960.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 0a4ffdd1d2a7..5e5af898f7f8 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -857,9 +857,9 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, if (pll_div.k) { reg |= 0x20; - snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f); - snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff); - snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff); + snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); + snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); + snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); } snd_soc_write(codec, WM8960_PLL1, reg); |