diff options
| author | Dong Aisheng <b29396@freescale.com> | 2011-07-20 11:41:45 +0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-08-23 08:56:14 +0200 |
| commit | b00d533ebc9e60f63697869e5c2b360ee842ac0a (patch) | |
| tree | 1221876d5e520c8df09d8d4c726b5949eec300be | |
| parent | ce9b8e6f9f8bf363c30024ba900e75a1af734742 (diff) | |
ARM: mxs: correct the using of frac div for saif
According to spec, set to 1 is the enable of fractional devide
or the clock can not be generated properly.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-mxs/clock-mx28.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 7b3657b240c8..7954013bd32f 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -710,11 +710,11 @@ static int clk_misc_init(void) /* SAIF has to use frac div for functional operation */ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); - reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN; __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); - reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN; + reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN; __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); /* |