ARM: dts: msm: add PM8005 PMIC peripheral devices for msmcobalt

Add a dtsi file which specifies the peripherals found in the
PM8005 PMIC chip.  Include this new file for msmcobalt boards
since they make use of this chip.

Change-Id: I6620cf1fd5ec4181b7ce79bc97039af954dc324e
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>

2 files changed, 102 insertions, 4 deletions

diff --git a/arch/arm/boot/dts/qcom/msm-pm8005.dtsi b/arch/arm/boot/dts/qcom/msm-pm8005.dtsi
new file mode 100644
index 000000000000..a7e57cbe1480
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msm-pm8005.dtsi
@@ -0,0 +1,96 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&spmi_bus {
+	qcom,pm8005@4 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		pm8005_revid: qcom,revid@100 {
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100 0x100>;
+		};
+
+		pm8005_gpios: gpios {
+			compatible = "qcom,qpnp-pin";
+			gpio-controller;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			label = "pm8005-gpio";
+
+			gpio@c000 {
+				reg = <0xc000 0x100>;
+				qcom,pin-num = <1>;
+				status = "disabled";
+			};
+
+			gpio@c100 {
+				reg = <0xc100 0x100>;
+				qcom,pin-num = <2>;
+				status = "disabled";
+			};
+
+			gpio@c200 {
+				reg = <0xc200 0x100>;
+				qcom,pin-num = <3>;
+				status = "disabled";
+			};
+
+			gpio@c300 {
+				reg = <0xc300 0x100>;
+				qcom,pin-num = <4>;
+				status = "disabled";
+			};
+		};
+	};
+
+	qcom,pm8005@5 {
+		compatible ="qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		regulator@1400 {
+			compatible = "qcom,qpnp-regulator";
+			reg = <0x1400 0x100>;
+			regulator-name = "pm8005_s1";
+			status = "disabled";
+		};
+
+		regulator@1700 {
+			compatible = "qcom,qpnp-regulator";
+			reg = <0x1700 0x100>;
+			regulator-name = "pm8005_s2";
+			status = "disabled";
+		};
+
+		regulator@1a00 {
+			compatible = "qcom,qpnp-regulator";
+			reg = <0x1a00 0x100>;
+			regulator-name = "pm8005_s3";
+			status = "disabled";
+		};
+
+		regulator@1d00 {
+			compatible = "qcom,qpnp-regulator";
+			reg = <0x1d00 0x100>;
+			regulator-name = "pm8005_s4";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index dd842484eca6..8a86716ea3c3 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -2154,18 +2154,20 @@
 	status = "ok";
 };
 
+#include "msm-pmcobalt.dtsi"
+#include "msm-pmicobalt.dtsi"
+#include "msm-pm8005.dtsi"
+#include "msm-pmcobalt-rpm-regulator.dtsi"
+#include "msmcobalt-regulator.dtsi"
+
 #include "msmcobalt-pm.dtsi"
 #include "msm-arm-smmu-cobalt.dtsi"
 #include "msmcobalt-ion.dtsi"
-#include "msm-pmcobalt-rpm-regulator.dtsi"
-#include "msmcobalt-regulator.dtsi"
 #include "msmcobalt-camera.dtsi"
 #include "msmcobalt-vidc.dtsi"
 #include "msmcobalt-coresight.dtsi"
 #include "msmcobalt-bus.dtsi"
 #include "msmcobalt-gpu.dtsi"
-#include "msm-pmcobalt.dtsi"
-#include "msm-pmicobalt.dtsi"
 #include "msmcobalt-pinctrl.dtsi"
 #include "msm-audio-lpass.dtsi"
 #include "msmcobalt-audio.dtsi"