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| author | Linux Build Service Account <lnxbuild@quicinc.com> | 2017-05-27 18:12:13 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-05-27 18:12:13 -0700 |
| commit | d11a00dbfa74cb0d6939a9ba1014d384080cddac (patch) | |
| tree | 0c3d56bc45c2a3e8a2d4b23e87eb1095f6446ff5 | |
| parent | ce48f56032a340cbc6d9423e6cec3ef4ec15bfc6 (diff) | |
| parent | 5d1a2710565c17f07c22a2816c5856180a5a78c8 (diff) | |
Merge "msm: mdss: ensure clocks are on till pixel transfer is completed"
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi_host.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dsi_host.c b/drivers/video/fbdev/msm/mdss_dsi_host.c index 007272dabae2..f0fb791a7b8d 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_host.c +++ b/drivers/video/fbdev/msm/mdss_dsi_host.c @@ -165,7 +165,14 @@ void mdss_dsi_clk_req(struct mdss_dsi_ctrl_pdata *ctrl, MDSS_XLOG(ctrl->ndx, enable, ctrl->mdp_busy, current->pid, client); - if (enable == 0) { + /* + * ensure that before going into ecg or turning + * off the clocks, cmd_mdp_busy is not true. During a + * race condition, clocks are turned off and so the + * isr for cmd_mdp_busy does not get cleared in hw. + */ + if (enable == MDSS_DSI_CLK_OFF || + enable == MDSS_DSI_CLK_EARLY_GATE) { /* need wait before disable */ mutex_lock(&ctrl->cmd_mutex); mdss_dsi_cmd_mdp_busy(ctrl); |