diff options
| author | Rajesh Kemisetti <rajeshk@codeaurora.org> | 2016-01-26 18:49:50 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:20:11 -0700 |
| commit | dcd10b0229953681f104130b44c9d2736aa5c742 (patch) | |
| tree | 0cefbf802750c16ef950bf20f019680771d75fee | |
| parent | 981288388203c0c520d997071e28992a3a467e8b (diff) | |
msm: kgsl: Enable content protection for A506
Enable content protection for A506 from gpulist.
Also, skip scm call to program CP secure ucode base
registers since A506 supports retention for these
registers.
Change-Id: I48a0f04826430bfb927c755c176255be45199b26
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
| -rw-r--r-- | drivers/gpu/msm/adreno-gpulist.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/msm/adreno.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/msm/adreno_a5xx.c | 6 |
3 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index c03484f0b7fb..78832b8a9712 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2002,2007-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2002,2007-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -216,9 +216,11 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .major = 0, .minor = 6, .patchid = ANY_ID, - .features = ADRENO_PREEMPTION | ADRENO_64BIT, + .features = ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION, .pm4fw_name = "a530_pm4.fw", .pfpfw_name = "a530_pfp.fw", + .zap_name = "a506_zap", .gpudev = &adreno_a5xx_gpudev, .gmem_size = (SZ_128K + SZ_8K), .num_protected_regs = 0x20, diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 7a96347b863e..8a6aae3472f1 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -109,6 +109,8 @@ #define ADRENO_LM BIT(8) /* The core uses 64 bit GPU addresses */ #define ADRENO_64BIT BIT(9) +/* The GPU supports retention for cpz registers */ +#define ADRENO_CPZ_RETENTION BIT(10) /* * Adreno GPU quirks - control bits for various workarounds diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c index ca4e4d5c4a1d..0b2513cd7abf 100644 --- a/drivers/gpu/msm/adreno_a5xx.c +++ b/drivers/gpu/msm/adreno_a5xx.c @@ -2498,9 +2498,11 @@ static int a5xx_microcode_load(struct adreno_device *adreno_dev, /* * Resume call to write the zap shader base address into the - * appropriate register + * appropriate register, + * skip if retention is supported for the CPZ register */ - if (zap_ucode_loaded) { + if (zap_ucode_loaded && !(ADRENO_FEATURE(adreno_dev, + ADRENO_CPZ_RETENTION))) { int ret; struct scm_desc desc = {0}; |