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| author | Tony Truong <truong@codeaurora.org> | 2015-04-27 13:12:55 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:09:15 -0700 |
| commit | e20be88c34e2d45c2eab6af4d05b55ecaf3ad1b5 (patch) | |
| tree | 12559b180315658fa19a7e1e06d024dc98d6d33b | |
| parent | 25314fd288c19293fb7ac2862d14531a6c6e4941 (diff) | |
Documentation: devicetree: add iommus entry for PCIe
PCIe on some targets require the iommus device tree entry.
Therefore, add this device tree entry to the PCIe
documentation.
Change-Id: Iec6c4cfcd5e51d6aa1259bb826fe60d131072170
Signed-off-by: Tony Truong <truong@codeaurora.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/msm_pcie.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt index 343ca2da0579..9033c4bb90d7 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt @@ -76,6 +76,9 @@ Optional Properties: - qcom,msi-gicm-addr: MSI address for GICv2m. - qcom,msi-gicm-base: MSI IRQ base for GICv2m. - qcom,ext-ref-clk: The reference clock is external. + - iommus: the phandle and stream IDs for the SMMU used by this root + complex. This should be used in separate nodes from the main root + complex nodes, and is the only property needed in that case. - qcom,common-phy: There is a common phy for all the Root Complexes. - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become stable after power on, before de-assert the PERST to the endpoint. @@ -217,6 +220,8 @@ Example: qcom,common-phy; qcom,ep-latency = <100>; + iommus = <&anoc0_smmu>; + qcom,msm-bus,name = "pcie0"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; |