diff options
| author | Tony Truong <truong@codeaurora.org> | 2016-05-20 12:11:49 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-03-23 00:29:10 -0700 |
| commit | eae5b8fa98b3b8841378baf2bf57b1ea85347f43 (patch) | |
| tree | 2adca5d4956e59d4e0d5192323c7e800aa7423a0 | |
| parent | e823a55d473519968ceb166e106983aeabde8a89 (diff) | |
ARM: dts: msm: disable L1/L1ss for all PCIe on MSM8996 AUTO
Link state L1 and L1ss is not supported on MSM8996 AUTO
platforms. Thus, disable L1 and L1ss for all PCIe cores
on these platforms.
Change-Id: Ifd95e1bba9c895ea35e50545bd6ad93e42fca5e6
Signed-off-by: Tony Truong <truong@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi | 16 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi | 12 |
2 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi index 637d6ddf27fe..464ee6a77134 100644 --- a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi @@ -44,9 +44,25 @@ status = "ok"; }; +&pcie0 { + /delete-property/ qcom,l1-supported; + /delete-property/ qcom,l1ss-supported; + /delete-property/ qcom,aux-clk-sync; +}; + &pcie1 { qcom,msi-gicm-addr = <0x09BD0040>; qcom,msi-gicm-base = <0x240>; + + /delete-property/ qcom,l1-supported; + /delete-property/ qcom,l1ss-supported; + /delete-property/ qcom,aux-clk-sync; +}; + +&pcie2 { + /delete-property/ qcom,l1-supported; + /delete-property/ qcom,l1ss-supported; + /delete-property/ qcom,aux-clk-sync; }; &uartblsp2dm1 { diff --git a/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi index d1b494ca00f7..ab5237a833bf 100644 --- a/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi @@ -969,10 +969,19 @@ /delete-property/ vin-supply; }; +&pcie0 { + /delete-property/ qcom,l1-supported; + /delete-property/ qcom,l1ss-supported; + /delete-property/ qcom,aux-clk-sync; +}; + &pcie1 { qcom,msi-gicm-addr = <0x09BD0040>; qcom,msi-gicm-base = <0x240>; + /delete-property/ qcom,l1-supported; + /delete-property/ qcom,l1ss-supported; + /delete-property/ qcom,aux-clk-sync; /delete-property/ qcom,ep-wakeirq; }; @@ -980,6 +989,9 @@ perst-gpio = <&tlmm 90 0>; wake-gpio = <&tlmm 54 0>; + /delete-property/ qcom,l1-supported; + /delete-property/ qcom,l1ss-supported; + /delete-property/ qcom,aux-clk-sync; /delete-property/ qcom,ep-wakeirq; }; |