diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-12-26 08:58:27 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-12-26 08:58:26 -0800 |
| commit | f66cd22d6d9936bee3399f99cada5fa0f7c29e73 (patch) | |
| tree | f7bbc2082bf4e58911c5c0a1f324019f2f1dd946 | |
| parent | 7c77d8252afe42286496d7d84dc4fa59c2421365 (diff) | |
| parent | da422925cd8f4ebdbc220c3add5e9e349f11b1fe (diff) | |
Merge "ARM: dts: msm: Add support for CPU clocks for msmfalcon"
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon.dtsi | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index c43781f3939e..b57e7d033c70 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -1083,6 +1083,101 @@ }; }; + clock_cpu: qcom,clk-cpu-falcon@179c0000 { + compatible = "qcom,clk-cpu-osm"; + status = "disabled"; + reg = <0x179c0000 0x4000>, <0x17916000 0x1000>, + <0x17816000 0x1000>, <0x179d1000 0x1000>, + <0x00784130 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "perfcl_efuse"; + + /* ToDo: Add power and perf supply rails */ + + interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwrcl-irq", "perfcl-irq"; + + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 633600000 0x05040021 0x03200020 0x1 1 >, + < 902400000 0x0404002f 0x04260026 0x1 2 >, + < 1113600000 0x0404003a 0x052e002e 0x2 3 >, + < 1401600000 0x04040049 0x073a003a 0x2 4 >, + < 1536000000 0x04040050 0x08400040 0x3 5 >, + < 1747200000 0x0404005b 0x09480048 0x3 6 >, + < 1843200000 0x04040060 0x094c004c 0x3 7 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 1113600000 0x0404003a 0x052e002e 0x1 1 >, + < 1401600000 0x04040049 0x073a003a 0x2 2 >, + < 1747200000 0x0404005b 0x09480048 0x2 3 >, + < 1958400000 0x04040066 0x0a510051 0x3 4 >, + < 2150400000 0x04040070 0x0b590059 0x3 5 >, + < 2457600000 0x04040080 0x0c660066 0x3 6 >; + + qcom,perfcl-speedbin1-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 1113600000 0x0404003a 0x052e002e 0x1 1 >, + < 1401600000 0x04040049 0x073a003a 0x2 2 >, + < 1747200000 0x0404005b 0x09480048 0x2 3 >, + < 1958400000 0x04040066 0x0a510051 0x3 4 >, + < 2150400000 0x04040070 0x0b590059 0x3 5 >, + < 2208000000 0x04040073 0x0b5c005c 0x3 6 >; + + qcom,up-timer = <1000 1000>; + qcom,down-timer = <1000 1000>; + qcom,pc-override-index = <0 0>; + qcom,set-ret-inactive; + qcom,enable-llm-freq-vote; + qcom,llm-freq-up-timer = <327675 327675>; + qcom,llm-freq-down-timer = <327675 327675>; + qcom,enable-llm-volt-vote; + qcom,llm-volt-up-timer = <327675 327675>; + qcom,llm-volt-down-timer = <327675 327675>; + qcom,cc-reads = <10>; + qcom,cc-delay = <5>; + qcom,cc-factor = <100>; + qcom,osm-clk-rate = <200000000>; + qcom,xo-clk-rate = <19200000>; + + qcom,l-val-base = <0x17916004 0x17816004>; + qcom,apcs-itm-present = <0x179d143c 0x179d143c>; + qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; + qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; + qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; + qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; + qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; + + qcom,apm-threshold-voltage = <832000>; + qcom,boost-fsm-en; + qcom,safe-fsm-en; + qcom,ps-fsm-en; + qcom,droop-fsm-en; + qcom,wfx-fsm-en; + qcom,pc-fsm-en; + + qcom,pwrcl-apcs-mem-acc-cfg = + <0x179d1360 0x179d1364 0x179d1364>; + qcom,perfcl-apcs-mem-acc-cfg = + <0x179d1368 0x179d136C 0x179d1370>; + qcom,pwrcl-apcs-mem-acc-val = + <0x00000000 0x80000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000001 0x00000001>; + qcom,perfcl-apcs-mem-acc-val = + <0x00000000 0x00000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000001>; + + clock-names = "aux_clk", "xo_a"; + clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>, + <&clock_rpmcc RPM_XO_A_CLK_SRC>; + + #clock-cells = <1>; + }; + sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdhci-msm-v5"; reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>; |