diff options
author | Devesh Jhunjhunwala <deveshj@codeaurora.org> | 2016-01-26 12:47:30 -0800 |
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committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 10:58:50 -0700 |
commit | f910a321bdf2bb596db433a921e53267683dcb24 (patch) | |
tree | 6e73cf85d4fad830f3bb7df978201fb20b20ac71 | |
parent | de8b5072ec6b8e5b27b227bcda972e5dd592ec70 (diff) |
clk: msm: Add documentation for gdsc regulator driver
This is a snapshot of gdsc-regulator documentation as of
msm-3.18 commit:
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of
kernel.lnx.3.18-151201.)
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
-rw-r--r-- | Documentation/devicetree/bindings/regulator/gdsc-regulator.txt | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt b/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt new file mode 100644 index 000000000000..b4ef2566727b --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt @@ -0,0 +1,57 @@ +Qualcomm Global Distributed Switch Controller (GDSC) Regulator Driver + +The GDSC driver, implemented under the regulator framework, is responsible for +safely collapsing and restoring power to peripheral cores on chipsets like +msm8974 for power savings. + +Required properties: + - compatible: Must be "qcom,gdsc" + - regulator-name: A string used as a descriptive name for regulator outputs + - reg: The address of the GDSCR register + +Optional properties: + - parent-supply: phandle to the parent supply/regulator node + - clock-names: List of string names for core clocks + - qcom,retain-mem: Presence denotes a hardware requirement to leave the + forced core memory retention signals in the core's clock + branch control registers asserted. + - qcom,retain-periph: Presence denotes a hardware requirement to leave the + forced periph memory retention signal in the core's clock + branch control registers asserted. + - qcom,skip-logic-collapse: Presence denotes a requirement to leave power to + the core's logic enabled. + - qcom,support-hw-trigger: Presence denotes a hardware feature to switch + on/off this regulator based on internal HW signals + to save more power. + - qcom,enable-root-clk: Presence denotes that the clocks in the "clocks" + property are required to be enabled before gdsc is + turned on and disabled before turning off gdsc. This + will be used in subsystems where reset is synchronous + and root clk is active without sw being aware of its + state. The clock-name which denotes the root clock + should be named as "core_root_clk". + - qcom,force-enable-root-clk: If set, denotes that the root clock should be + force enabled before turning on the GDSC and then be + immediately force disabled. Likewise for GDSC disable. + This is used in cases where the core root clock needs + to be force-enabled prior to turning on the core. The + clock-name which denotes the root clock should be + "core_root_clk". + - qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition + delay after halting clock in the collapsible core. + - reg-names: Names of the bases for the above "reg" registers. + Ex. "base", "domain_addr". + - qcom,no-status-check-on-disable: Do not poll the status bit when GDSC + is disabled. + - qcom,disallow-clear: Presence denotes the periph & core memory will not be + cleared, unless the required subsystem does not invoke + the api which will allow clearing the bits. + +Example: + gdsc_oxili_gx: qcom,gdsc@fd8c4024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_gx"; + parent-supply = <&pm8841_s4>; + reg = <0xfd8c4024 0x4>; + clock-names = "core_clk"; + }; |