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authorArchana Sathyakumar <asathyak@codeaurora.org>2015-03-13 14:32:17 -0600
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-22 11:07:28 -0700
commit405157e0d53c33347a98ebffe6b3bd53b7330104 (patch)
tree9d0061d16d3edcd3f10fb6a737362bb06cff34d8
parent8cbe96494f90c7e6aac1c585ea4c701d9780db73 (diff)
irqchip: gic: Add arch extension to GIC v3
Propagate platform arch extension to call into platform specific callback functions for GIC operations. Change-Id: Ief42e9812e0593572bbde0fbe5e641eb9b3f5412 Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org> Conflicts: drivers/irqchip/irq-gic-common.c drivers/irqchip/irq-gic-common.h drivers/irqchip/irq-gic-v3.c drivers/irqchip/irq-gic.c
-rw-r--r--drivers/irqchip/irq-gic-common.c13
-rw-r--r--drivers/irqchip/irq-gic-v3.c18
-rw-r--r--drivers/irqchip/irq-gic.c9
3 files changed, 32 insertions, 8 deletions
diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c
index f174ce0ca361..5f8b8759672a 100644
--- a/drivers/irqchip/irq-gic-common.c
+++ b/drivers/irqchip/irq-gic-common.c
@@ -32,6 +32,19 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
}
}
+/*
+ * Supported arch specific GIC irq extension.
+ * Default make them NULL.
+ */
+struct irq_chip gic_arch_extn = {
+ .irq_eoi = NULL,
+ .irq_mask = NULL,
+ .irq_unmask = NULL,
+ .irq_retrigger = NULL,
+ .irq_set_type = NULL,
+ .irq_set_wake = NULL,
+};
+
int gic_configure_irq(unsigned int irq, unsigned int type,
void __iomem *base, void (*sync_access)(void))
{
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 0ebd9b00db04..4ddeec9834f5 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -190,6 +190,9 @@ static void gic_poke_irq(struct irq_data *d, u32 offset)
static void gic_mask_irq(struct irq_data *d)
{
+ if (gic_arch_extn.irq_mask)
+ gic_arch_extn.irq_mask(d);
+
gic_poke_irq(d, GICD_ICENABLER);
}
@@ -210,6 +213,8 @@ static void gic_eoimode1_mask_irq(struct irq_data *d)
static void gic_unmask_irq(struct irq_data *d)
{
+ if (gic_arch_extn.irq_unmask)
+ gic_arch_extn.irq_unmask(d);
gic_poke_irq(d, GICD_ISENABLER);
}
@@ -267,9 +272,17 @@ static int gic_irq_get_irqchip_state(struct irq_data *d,
return 0;
}
+static void gic_disable_irq(struct irq_data *d)
+{
+ if (gic_arch_extn.irq_disable)
+ gic_arch_extn.irq_disable(d);
+}
static void gic_eoi_irq(struct irq_data *d)
{
+ if (gic_arch_extn.irq_eoi)
+ gic_arch_extn.irq_eoi(d);
+
gic_write_eoir(gic_irq(d));
}
@@ -307,6 +320,9 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
rwp_wait = gic_dist_wait_for_rwp;
}
+ if (gic_arch_extn.irq_set_type)
+ gic_arch_extn.irq_set_type(d, type);
+
return gic_configure_irq(irq, type, base, rwp_wait);
}
@@ -678,6 +694,7 @@ static struct irq_chip gic_chip = {
.irq_eoi = gic_eoi_irq,
.irq_set_type = gic_set_type,
.irq_set_affinity = gic_set_affinity,
+ .irq_disable = gic_disable_irq,
.irq_get_irqchip_state = gic_irq_get_irqchip_state,
.irq_set_irqchip_state = gic_irq_set_irqchip_state,
.flags = IRQCHIP_SET_TYPE_MASKED,
@@ -906,6 +923,7 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
its_init(node, &gic_data.rdists, gic_data.domain);
+ gic_chip.flags |= gic_arch_extn.flags;
gic_smp_init();
gic_dist_init();
gic_cpu_init();
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 087c31ab3326..fb940e92b64e 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -102,14 +102,7 @@ static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
* Supported arch specific GIC irq extension.
* Default make them NULL.
*/
-struct irq_chip gic_arch_extn = {
- .irq_eoi = NULL,
- .irq_mask = NULL,
- .irq_unmask = NULL,
- .irq_retrigger = NULL,
- .irq_set_type = NULL,
- .irq_set_wake = NULL,
-};
+extern struct irq_chip gic_arch_extn;
#ifndef MAX_GIC_NR
#define MAX_GIC_NR 1