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authorTony Truong <truong@codeaurora.org>2016-05-23 15:05:58 -0700
committerKyle Yan <kyan@codeaurora.org>2016-05-24 17:55:34 -0700
commit15ed672eb9e0e672d21ccfaabc89a00d6f940580 (patch)
tree23e331212054e9bdb2183255c22f35180a41d00c /Documentation/devicetree
parentc3ab6387ba178f77ad19d8ded1f0b59ee9700e80 (diff)
msm: pcie: add support to get PCIe port PHY sequence from DT
PCIe PHY varies between each chipset. Thus, the port PHY init sequence on each of these chipsets are also different. Therefore, add the support to read PCIe port PHY init sequence from devicetree. Change-Id: I92969b7b59a64018b80470566567887248ced2bd Signed-off-by: Tony Truong <truong@codeaurora.org>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/pci/msm_pcie.txt10
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt
index c8e634617edb..4b5a6b4af789 100644
--- a/Documentation/devicetree/bindings/pci/msm_pcie.txt
+++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt
@@ -75,6 +75,9 @@ Optional Properties:
- qcom,pcie-phy-ver: version of PCIe PHY.
- qcom,phy-sequence: The initialization sequence to bring up the PCIe PHY.
Should be specified in groups (offset, value, delay).
+ - qcom,port-phy-sequence: The initialization sequence to bring up the
+ PCIe port PHY.
+ Should be specified in groups (offset, value, delay).
- qcom,use-19p2mhz-aux-clk: The frequency of PCIe AUX clock is 19.2MHz.
- qcom,ep-wakeirq: The endpoint will issue wake signal when it is up, and the
root complex has the capability to enumerate the endpoint for this case.
@@ -197,6 +200,13 @@ Example:
0x15c 0x06 0x00
0x090 0x01 0x00
0x808 0x03 0x00>;
+ qcom,port-phy-sequence = <0x804 0x01 0x00
+ 0x034 0x14 0x00
+ 0x138 0x30 0x00
+ 0x048 0x0f 0x00
+ 0x15c 0x06 0x00
+ 0x090 0x01 0x00
+ 0x808 0x03 0x00>;
perst-gpio = <&msmgpio 70 0>;
wake-gpio = <&msmgpio 69 0>;
clkreq-gpio = <&msmgpio 68 0>;