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| author | Prasad Sodagudi <psodagud@codeaurora.org> | 2015-07-28 10:01:04 +0530 |
|---|---|---|
| committer | Srinivas Ramana <sramana@codeaurora.org> | 2016-11-01 18:02:29 +0530 |
| commit | 488460b4152924659d24d4a8e7043ec4568a4738 (patch) | |
| tree | 808e29d18291d417eba85b62691d6e42296d14f5 /Documentation | |
| parent | 0645a625acf8a125df3e8867457eab9b20ba9f83 (diff) | |
ARM: dts: msm: Add qcom,dump-size entry for dumping CPU L1/L2 caches
Update arm cache documentation about qcom,dump-size to dump
the CPU L1/L2 caches in order to analyze data corruption.
Change-Id: Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cache.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt index b27cedf485f8..a9594f026506 100644 --- a/Documentation/devicetree/bindings/arm/cache.txt +++ b/Documentation/devicetree/bindings/arm/cache.txt @@ -64,6 +64,14 @@ This document provides the device tree bindings for ARM architected caches. bindings of power controller specified by the phandle [5]. + - qcom,dump-size + Usage: Optional + Value type: <integer> + Definition: The memory size needed to contain a copy of the + cache data and associated tag ram. + size = nways * nsets * (bytes per cache line + + bytes tag ram per line) + Example(dual-cluster big.LITTLE system 32-bit) cpus { |