drm/msm/sde: add driver for sde support

Initial DRM/KMS driver to support snapdragon display engine.

Change-Id: I2f93d7cd24acf77359682f90b6b9647017ed62ba
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Signed-off-by: Krishna Srinivas Kundurthi <kskund@codeaurora.org>

1 files changed, 55 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
new file mode 100644
index 000000000000..8ec9f78346d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -0,0 +1,55 @@
+Qualcomm Technologies, Inc. SDE KMS
+
+Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user
+interface to different panel interfaces. SDE driver is the core of
+display subsystem which manage all data paths to different panel interfaces.
+
+Required properties
+- compatible: Must be "qcom,sde-kms"
+- reg: Offset and length of the register set for the device.
+- reg-names : Names to refer to register sets related to this device
+- clocks: List of Phandles for clock device nodes
+    needed by the device.
+- clock-names: List of clock names needed by the device.
+- mmagic-supply: Phandle for mmagic mdss supply regulator device node.
+- vdd-supply: Phandle for vdd regulator device node.
+- interrupt-parent: Must be core interrupt controller.
+- interrupts: Interrupt associated with MDSS.
+- interrupt-controller: Mark the device node as an interrupt controller.
+- #interrupt-cells: Should be one. The first cell is interrupt number.
+- iommus: Specifies the SID's used by this context bank.
+
+Please refer to ../../interrupt-controller/interrupts.txt for a general
+description of interrupt bindings.
+
+Example:
+  mdss_mdp: qcom,mdss_mdp@900000 {
+    compatible = "qcom,sde-kms";
+    reg = <0x00900000 0x90000>,
+          <0x009b0000 0x1040>,
+          <0x009b8000 0x1040>;
+    reg-names = "mdp_phys",
+      "vbif_phys",
+      "vbif_nrt_phys";
+    clocks = <&clock_mmss clk_mdss_ahb_clk>,
+      <&clock_mmss clk_mdss_axi_clk>,
+      <&clock_mmss clk_mdp_clk_src>,
+      <&clock_mmss clk_mdss_mdp_vote_clk>,
+      <&clock_mmss clk_smmu_mdp_axi_clk>,
+      <&clock_mmss clk_mmagic_mdss_axi_clk>,
+      <&clock_mmss clk_mdss_vsync_clk>;
+    clock-names = "iface_clk",
+      "bus_clk",
+      "core_clk_src",
+      "core_clk",
+      "iommu_clk",
+      "mmagic_clk",
+      "vsync_clk";
+    mmagic-supply = <&gdsc_mmagic_mdss>;
+    vdd-supply = <&gdsc_mdss>;
+    interrupt-parent = <&intc>;
+    interrupts = <0 83 0>;
+    interrupt-controller;
+    #interrupt-cells = <1>;
+    iommus = <&mdp_smmu 0>;
+  };