diff options
| author | Vijayavardhan Vennapusa <vvreddy@codeaurora.org> | 2014-05-08 13:47:50 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:06:31 -0700 |
| commit | 567c83ebc7e73ea9dde355fa52e03be13e45d43f (patch) | |
| tree | d0231b11e2da0b9028a4af3437a8ab154c0bc4f5 /Documentation | |
| parent | 01edad63c9152c1ac3aae8edbf8d373f18dbcd07 (diff) | |
USB: dwc3: Add support for fixing superspeed enumeration issue
Setting SSPHY SUSP bit (bit 17) in GUSB3PIPECTL(0) register
might cause device enumerating at high speed mode instead of
superspeed mode on some platforms. Hence add workaround by
clearing the SSPHY SUSP bit during disconnect and setting it
after it is configured to fix this enumeration issue on those
platforms.
Also add support for disabling U1 and U2 low power modes which
could also affect this enumeration issue.
CRs-Fixed: 637902
Change-Id: I8668ced09a88b77f37265ab15e89fa9e964bfbe9
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
[jackp@codeaurora.org: only add u1/u2 disable bits]
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/usb/dwc3.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 5d038e814203..ead827a714f5 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -48,6 +48,8 @@ Optional properties: fladj_30mhz_sdbnd signal is invalid or incorrect. - snps,nominal-elastic-buffer: When set, the nominal elastic buffer setting is used. By default, the half-full setting is used. + - snps,usb3-u1u2-disable: If present, disable u1u2 low power modes for DWC3 core + controller in SS mode. This is usually a subnode to DWC3 glue to which it is connected. @@ -57,4 +59,5 @@ dwc3@4a030000 { interrupts = <0 92 4> usb-phy = <&usb2_phy>, <&usb3,phy>; tx-fifo-resize; + snps,usb3-u1u2-disable; }; |