input: move DT binding documentation for qpnp-power-on to input

qpnp-power-on driver have been moved to drivers/input and no
longer present under drivers/platform/msm. Move the DT binding
documentation as well there.

While at it, fix the indentation so that it pass checkpatch.

Change-Id: I32f416d32a57d7c447563d26e4dad24605cdce50
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>

1 files changed, 65 insertions, 52 deletions

diff --git a/Documentation/devicetree/bindings/platform/msm/qpnp-power-on.txt b/Documentation/devicetree/bindings/input/qpnp-power-on.txt
index 6644673eef85..5b364d0a77ba 100644
--- a/Documentation/devicetree/bindings/platform/msm/qpnp-power-on.txt
+++ b/Documentation/devicetree/bindings/input/qpnp-power-on.txt
@@ -3,27 +3,30 @@ Qualcomm QPNP power-on
 The qpnp-power-on is a driver which supports the power-on(PON)
 peripheral on Qualcomm PMICs. The supported functionality includes
 power on/off reason, key press/release detection, PMIC reset configurations
-and other PON specifc features. The PON module supports multiple physical
+and other PON specific features. The PON module supports multiple physical
 power-on (KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources.
 This peripheral is connected to the host processor via the SPMI interface.
 
 Required properties:
 - compatible:	Must be "qcom,qpnp-power-on"
-- reg:		Specifies the SPMI address and size for this PON (power-on) peripheral
+- reg:		Specifies the SPMI address and size for this PON (power-on)
+		peripheral.
 - interrupts:	Specifies the interrupt associated with PON.
-- interrupt-names:	Specify the interrupt names associated with interrupts. Must be
-			one of "kpdpwr", "kpdpwr-bark", "resin", "resin-bark", "cblpwr",
-			"kpdpwr-resin-bark". Bark interrupts are associated with system
-			reset configuration to allow default reset configuration to be
-			activated. If system reset configuration is not supported then
-			bark interrupts are nops. Additionally, the "pmic-wd-bark"
-			interrupt can be added if the system needs to handle PMIC
-			watch dog barks.
+- interrupt-names:	Specify the interrupt names associated with interrupts.
+			Must be one of "kpdpwr", "kpdpwr-bark", "resin",
+			"resin-bark", "cblpwr", "kpdpwr-resin-bark".Bark
+			interrupts are associated with system reset
+			configuration to allow default reset configuration to
+			be activated. If system reset configuration is not
+			supported then bark interrupts are nops. Additionally,
+			the "pmic-wd-bark" interrupt can be added if the system
+			needs to handle PMIC watch dog barks.
 
 Optional properties:
 - qcom,pon-dbc-delay		The debounce delay for the power-key interrupt
-				specified in us. The value ranges from 2 seconds
-				to 1/64 of a second. Possible values are -
+				specified in us. The value ranges from 2
+				seconds to 1/64 of a second. Possible values
+				are:
 				- 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
 				- Intermediate value is rounded down to the
 				nearest valid value.
@@ -34,41 +37,48 @@ Optional properties:
 				to register.
 - qcom,system-reset		Specifies that this PON peripheral can be used
 				to reset the system. This property can only be
-				used by one device on the system. It is an error
-				to include it more than once.
+				used by one device on the system. It is an
+				error to include it more than once.
 - qcom,s3-debounce		The debounce delay for stage3 reset trigger in
 				secs. The values range from 0 to 128.
 - qcom,s3-src			The source for stage 3 reset. It can be one of
 				"kpdpwr", "resin", "kpdpwr-or-resin" or
 				"kpdpwr-and-resin". The default value is
 				"kpdpwr-and-resin".
-- qcom,uvlo-panic		If this property is present, the device will set to panic during reboot if this reboot is due to under voltage lock out
+- qcom,uvlo-panic		If this property is present, the device will
+				set to panic during reboot if this reboot is
+				due to under voltage lock out.
 - qcom,clear-warm-reset		Specifies that the WARM_RESET reason registers
-				need to be cleared for this target. The property
-				is used for the targets which have a hardware feature
-				to catch resets which aren't triggered by the MSM.
-				In such cases clearing WARM_REASON registers across
-				MSM resets keeps the registers in good state.
+				need to be cleared for this target. The
+				property is used for the targets which have a
+				hardware feature to catch resets which aren't
+				triggered by the MSM.
+				In such cases clearing WARM_REASON registers
+				across MSM resets keeps the registers in good
+				state.
 - qcom,secondary-pon-reset	Boolean property which indicates that the PON
-				peripheral is a secondary PON device which needs
-				to be configured during reset in addition to the
-				primary PON device that is configured for system
-				reset through qcom,system-reset property.
+				peripheral is a secondary PON device which
+				needs to be configured during reset in addition
+				to the primary PON device that is configured
+				for system reset through qcom,system-reset
+				property.
 				This should not be defined along with the
 				qcom,system-reset property.
-- qcom,store-hard-reset-reason	Boolean property which if set will store the hardware
-				reset reason to SOFT_RB_SPARE register of the core PMIC
-				PON peripheral.
-- qcom,warm-reset-poweroff-type		Poweroff type required to be configured on
-					PS_HOLD reset control register when the system
-					goes for warm reset. If this property is not
-					specified, then the default type, warm reset
-					will be configured to PS_HOLD reset control
-					register.
-- qcom,hard-reset-poweroff-type		Same description as qcom,warm-reset-poweroff-type
-					but this applies for the system hard reset case.
-- qcom,shutdown-poweroff-type		Same description as qcom,warm-reset-poweroff-type
-					but this applies for the system shutdown case.
+- qcom,store-hard-reset-reason	Boolean property which if set will store the
+				hardware reset reason to SOFT_RB_SPARE register
+				of the core PMIC PON peripheral.
+- qcom,warm-reset-poweroff-type	Poweroff type required to be configured on
+				PS_HOLD reset control register when the system
+				goes for warm reset. If this property is not
+				specified, then the default type, warm reset
+				will be configured to PS_HOLD reset control
+				register.
+- qcom,hard-reset-poweroff-type	Same description as qcom,warm-reset-poweroff-
+				type but this applies for the system hard reset
+				case.
+- qcom,shutdown-poweroff-type	Same description as qcom,warm-reset-poweroff-
+				type but this applies for the system shutdown
+				case.
 
 
 All the below properties are in the sub-node section (properties of the child
@@ -80,9 +90,9 @@ regulator configuration.
 Regulator sub-node required properties:
 - regulator-name		Regulator name for the PON regulator that
 				is being configured.
-- qcom,pon-spare-reg-addr	Register offset from the base address of the PON
-				peripheral that needs to be configured for the
-				regulator being controlled.
+- qcom,pon-spare-reg-addr	Register offset from the base address of the
+				PON peripheral that needs to be configured for
+				the regulator being controlled.
 - qcom,pon-spare-reg-bit	Bit position in the specified register that
 				needs to be configured for the regulator being
 				controlled.
@@ -102,27 +112,30 @@ PON sub-node optional properties:
 				reset functionality.
 				0 = Not supported
 				1 = Supported
-				If this property is not defined, then do not modify S2 reset
-				values.
-- qcom,use-bark                 Specify if this pon type needs to handle bark irq
-- linux,code                    The input key-code associated with the reset source.
-                                The reset source in its default configuration can be
-                                used to support standard keys.
-
-The below mentioned properties are required only when qcom,support-reset DT property is defined
-and is set to 1.
+				If this property is not defined, then do not
+				modify S2 reset values.
+- qcom,use-bark                 Specify if this pon type needs to handle bark
+				irq.
+- linux,code                    The input key-code associated with the reset
+				source.
+                                The reset source in its default configuration
+				can be used to support standard keys.
+
+The below mentioned properties are required only when qcom,support-reset DT
+property is defined and is set to 1.
 
 - qcom,s1-timer			The debounce timer for the BARK interrupt for
 				that reset source. Value is specified in ms.
-				Supported values are -
+				Supported values are:
 				- 0, 32, 56, 80, 128, 184, 272, 408, 608, 904
 				  1352, 2048, 3072, 4480, 6720, 10256
 - qcom,s2-timer			The debounce timer for the S2 reset specified
 				in ms. On the expiry of this timer, the PMIC
-				executes the reset sequence. Supported values -
+				executes the reset sequence.
+				Supported values are:
 				- 0, 10, 50, 100, 250, 500, 1000, 2000
 - qcom,s2-type			The type of reset associated with this source.
-				The supported resets are -
+				The supported resets are:
 				SOFT(0), WARM(1), SHUTDOWN(4), HARD(7)
 
 Example: