diff options
| author | Ram Chandrasekar <rkumbako@codeaurora.org> | 2016-04-29 09:51:33 -0600 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-05 15:05:55 -0700 |
| commit | 77bcd516088c63cc58d217e11830db39e668e4fd (patch) | |
| tree | 2fea93f8463291614b2a5b94e1cc7fab6feedea8 /Documentation | |
| parent | a492546c1c988e492b4bc061f2629cf73e81690d (diff) | |
msm: thermal: Make boot-up mitigation optional
For the targets with the LMH DCVSh mitigation, HLOS boot-up
mitigation is not required. So make the devicetree properties
related to boot-up mitigation as optional.
CRs-Fixed: 1010111
Change-Id: I7f254f579182effbc1f1a3d49c3c917d3c7af162
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/msm_thermal.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt b/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt index 4dac20bcda69..34001a9ef4e8 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt @@ -18,13 +18,13 @@ Required properties - qcom,sensor-id: The id of the TSENS sensor polled for temperature. Typically the sensor closest to CPU0. - qcom,poll-ms: Sampling interval to read sensor, in ms. -- qcom,limit-temp: Threshold temperature to start stepping CPU down, in degC. -- qcom,temp-hysteresis: Degrees C below threshold temperature to step CPU up. -- qcom,freq-step: Number of frequency steps to take on each CPU mitigation. Optional properties - reg: Physical address for uio mapping +- qcom,limit-temp: Threshold temperature to start stepping CPU down, in degC. +- qcom,temp-hysteresis: Degrees C below threshold temperature to step CPU up. +- qcom,freq-step: Number of frequency steps to take on each CPU mitigation. - qcom,core-limit-temp: Threshold temperature to start shutting down cores in degC - qcom,core-temp-hysteresis: Degrees C below which the cores will be brought |