diff options
| author | Subhash Jadavani <subhashj@codeaurora.org> | 2014-10-22 19:15:49 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 10:57:45 -0700 |
| commit | 851c8c3971e151330ebf74efffeb15223b9d5e0e (patch) | |
| tree | 3f7913ca4912252a932d64eb62f4d92d1032605a /Documentation | |
| parent | f1a31bcee020fb0d93113ce17bd29dc4ec4d1f8f (diff) | |
scsi: ufs-qcom: add support to control the device ref_clk
On Qualcomm platforms, there will be many consumers of the source clock
which also supply ref_clk to UFS Device. So even if generic UFS
driver (ufshcd) vote to turn off the source ref_clk, it's very likely that
device ref_clk is still running. Hence some of the qualcomm chipsets have
separate control bit to gate & ungate the UFS ref_clk to device. This
control bit is part of the TLMM register adddress space so it can't be
simulated at clock control bit which means UFS qcom driver has to manually
control this bit to gate or ungate the device ref_clk. This change adds
support for the same.
Change-Id: I3ee1187292eaadfdb552d33c2bb6f58922c9e501
[subhashj@codeaurora.org: resolved merge conflicts, dropped changes to
msm8994.dtsi]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts,
drop changes to include/linux/phy/phy-qcom-ufs.h]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/ufs/ufs-msm.txt | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/ufs/ufs-msm.txt b/Documentation/devicetree/bindings/ufs/ufs-msm.txt index 1e652f05ef0d..1b54b3c50ef3 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-msm.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-msm.txt @@ -10,7 +10,10 @@ Required properties: - compatible : compatible list, contains "qcom,ufs-phy-qmp-28nm" or "qcom,ufs-phy-qmp-20nm" according to the relevant phy in use -- reg : <registers mapping> +- reg : should contain PHY register address space (mandatory), + device PHY control register map (optional). +- reg-names : indicates various resources passed to driver (via reg proptery) by name. + Required "reg-names" is "phy_mem" and "dev_ref_clk_ctrl_mem" is optional. - #phy-cells : This property shall be set to 0 - vdda-phy-supply : phandle to main PHY supply for analog domain - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply @@ -23,7 +26,8 @@ Example: ufsphy1: ufsphy@0xfc597000 { compatible = "qcom,ufs-phy-qmp-28nm"; - reg = <0xfc597000 0x800>; + reg = <0xfc597000 0x800>, <0xfd512074 0x4>; + reg-names = "phy_mem", "dev_ref_clk_ctrl_mem"; #phy-cells = <0>; vdda-phy-supply = <&pma8084_l4>; vdda-pll-supply = <&pma8084_l12>; |