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authorLee Jones <lee.jones@linaro.org>2014-07-21 09:28:36 +0100
committerTejun Heo <tj@kernel.org>2014-07-21 08:18:17 -0400
commitaf64dce4cb3a848ece2431e1a18feebdcf57f444 (patch)
tree25e2b437421c0188a34c6733d52c641cbb7731e0 /Documentation
parentccfde50810ae916564765a2f8ee6d7163b025594 (diff)
ahci: st: Provide DT bindings for ST's SATA implementation
Cc: devicetree@vger.kernel.org Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'Documentation')
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+STMicroelectronics STi SATA controller
+
+This binding describes a SATA device.
+
+Required properties:
+ - compatible : Must be "st,sti-ahci"
+ - reg : Physical base addresses and length of register sets
+ - interrupts : Interrupt associated with the SATA device
+ - interrupt-names : Associated name must be; "hostc"
+ - resets : The power-down and soft-reset lines of SATA IP
+ - reset-names : Associated names must be; "pwr-dwn" and "sw-rst"
+ - clocks : The phandle for the clock
+ - clock-names : Associated name must be; "ahci_clk"
+ - phys : The phandle for the PHY device
+ - phy-names : Associated name must be; "ahci_phy"
+
+Example:
+
+ sata0: sata@fe380000 {
+ compatible = "st,sti-ahci";
+ reg = <0xfe380000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
+ interrupt-names = "hostc";
+ phys = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
+ phy-names = "ahci_phy";
+ resets = <&powerdown STIH416_SATA0_POWERDOWN>,
+ <&softreset STIH416_SATA0_SOFTRESET>;
+ reset-names = "pwr-dwn", "sw-rst";
+ clocks = <&clk_s_a0_ls CLK_ICN_REG>;
+ clock-names = "ahci_clk";
+ };