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authorZhiqiang Tu <ztu@codeaurora.org>2017-04-27 10:51:03 +0800
committerZhiqiang Tu <ztu@codeaurora.org>2017-05-02 08:59:16 +0800
commitb15484bc067e8c01e7cc2b186227f994547cf709 (patch)
tree88d900f03484d25dc8b5ad72b3706069adf1aa88 /Documentation
parentb1980b6bfedd0ac23e3b0320a8ed9bf7959e88bb (diff)
parent35ae76d2731e009ff57ccb33c766cb3086b65a51 (diff)
Merge remote-tracking branch 'remotes/quic/dev/msm-4.4-8996au' into msm-4.4
Conflicts: arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi drivers/gpu/drm/msm/Makefile Change-Id: Ief80c28ff1422fd71a0c3d2041531e2ab078ee7a Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt6
-rw-r--r--Documentation/devicetree/bindings/arm/msm/msm.txt1
-rw-r--r--Documentation/devicetree/bindings/cache/msm_cache_erp64.txt26
-rw-r--r--Documentation/devicetree/bindings/cache/msm_m4m_erp.txt15
-rw-r--r--Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt1
-rw-r--r--Documentation/devicetree/bindings/net/neutrino_avb.txt28
6 files changed, 77 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt b/Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt
index f3c6cc747710..bb74c167a324 100644
--- a/Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt
+++ b/Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt
@@ -8,6 +8,7 @@ PLL FMAXes etc.
Required properties:
- compatible: Must be either "qcom,cpu-clock-8996" or
"qcom,cpu-clock-8996-v3" or "qcom,cpu-clock-8996-pro"
+ or "qcom,cpu-clock-8996-auto"
- reg: Pairs of physical base addresses and region sizes of
memory mapped registers.
- reg-names: Names of the bases for the above registers. Expected
@@ -39,6 +40,11 @@ Required properties:
clock for the CBF.
- cbf-dev: The CBF cache device to which the OPP table for the
CBF clock domain will be added.
+
+Optional properties:
+- qcom,pwrcl-early-boot-freq: Power cluster early boot up frequency in HZ.
+- qcom,perfcl-early-boot-freq: Perf cluster early boot up frequency in HZ.
+
Example:
clock_cpu: qcom,cpu-clock-8996@ {
compatible = "qcom,cpu-clock-8996";
diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt
index 5647b22eede0..b6263a9665de 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm.txt
@@ -186,6 +186,7 @@ compatible = "qcom,apq8094-fluid"
compatible = "qcom,apq8094-liquid"
compatible = "qcom,apq8094-mtp"
compatible = "qcom,apq8094-dragonboard"
+compatible = "qcom,apq8096-adp"
compatible = "qcom,apq8096-cdp"
compatible = "qcom,apq8096-mtp"
compatible = "qcom,apq8096-dragonboard"
diff --git a/Documentation/devicetree/bindings/cache/msm_cache_erp64.txt b/Documentation/devicetree/bindings/cache/msm_cache_erp64.txt
new file mode 100644
index 000000000000..5dfb6d60529d
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/msm_cache_erp64.txt
@@ -0,0 +1,26 @@
+* MSM 64bit L0, L1, L2 and L3 cache error reporting driver
+
+Required properties:
+- compatible: Should be "qcom,kryo_cache_erp64"
+- reg: I/O address L3 hardware block.
+- interrupts: Should contain the L0/L1, L2 and L3 cache error interrupt number.
+- interrupt-names: Should contain the interrupt names "l1_irq", "l2_irq_info_0",
+ "l2_irq_info_1", "l2_irq_err_0", "l2_irq_err_1", "l3_irq".
+
+Example:
+ qcom,cache_erp64@6500000 {
+ compatible = "qcom,kryo_cache_erp64";
+ reg = <0x6500000 0x4000>;
+ /*
+ * PPI 0 for L0/L1
+ * SPI 1 for Cluster 1 L2 Info
+ * SPI 9 for Cluster 2 L2 Info
+ * SPI 2 for Cluster 1 L2 Error
+ * SPI 10 for Cluster 2 L2 Error
+ * SPI 17 for L3 error
+ */
+ interrupts = <1 0 0>, <0 1 0>, <0 9 0>, <0 2 0>, <0 10 0>,
+ <0 17 0>;
+ interrupt-names = "l1_irq", "l2_irq_info_0", "l2_irq_info_1",
+ "l2_irq_err_0", "l2_irq_err_1", "l3_irq";
+ };
diff --git a/Documentation/devicetree/bindings/cache/msm_m4m_erp.txt b/Documentation/devicetree/bindings/cache/msm_m4m_erp.txt
new file mode 100644
index 000000000000..5526f1188528
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/msm_m4m_erp.txt
@@ -0,0 +1,15 @@
+* MSM M4M error reporting driver
+
+Required properties:
+- compatible: Should be "qcom,m4m_erp".
+- reg: I/O address M4M hardware block.
+- interrupts: Should contain the M4M error interrupt number.
+- interrupt-names: Should contain the interrupt names "m4m_irq".
+
+Example:
+ qcom,m4m_erp64@9A40000 {
+ compatible = "qcom,m4m_erp";
+ reg = <0x9A40000 0x40000>;
+ interrupts = <0 22 0>;
+ interrupt-names = "m4m_irq";
+ };
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
index ce5ee56ada68..1f8458cd0659 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
@@ -563,6 +563,7 @@ Optional properites:
to a non-DSI interface.
- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name
is required if qcom,dba-panel is defined for the panel.
+- qcom,hdmi-mode: Indicates where current panel is HDMI mode, otherwise, it will be DVI mode.
- qcom,adjust-timer-wakeup-ms: An integer value to indicate the timer delay(in ms) to accommodate
s/w delay while configuring the event timer wakeup logic.
diff --git a/Documentation/devicetree/bindings/net/neutrino_avb.txt b/Documentation/devicetree/bindings/net/neutrino_avb.txt
new file mode 100644
index 000000000000..46c6a5208eba
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/neutrino_avb.txt
@@ -0,0 +1,28 @@
+* Neutrino Ethernet *
+This driver implements Ethernet driver for Neutrino ethernet controller
+Required properties:
+ - compatible: Should be "qcom,ntn_avb"
+ - ntn-rst-gpio: Neutrino reset GPIO
+ - vdd-ntn-hsic-supply: neutrino HSIC power supply
+ - vdd-ntn-pci-supply: PCIe core power supply
+ - vdd-ntn-io-supply: Neutrino IO power supply
+ - vdd-ntn-phy-supply: Ethernet Phy power supply
+ - vdd-ntn-core-supply: Neutrino core power supply
+ - pinctrl-names: should contain GPIO details
+ - pinctrl-0: Neutrino reset GPIO [this is from MSM]
+ - ntn-rst-delay-msec: dealy (msec) required after PCIe reset for stabilization
+ - ntn-rc-num: PCIe root complex number on which Neutrino is connected
+Example:
+ qcom,ntn_avb {
+ compatible = "qcom,ntn_avb";
+ ntn-rst-gpio = <&pm8994_gpios 13 0>;
+ vdd-ntn-hsic-supply = <&pm8994_l25>;
+ vdd-ntn-pci-supply = <&pm8994_s4>;
+ vdd-ntn-io-supply = <&pm8994_s4>;
+ vdd-ntn-phy-supply = <&pm8994_l9>;
+ vdd-ntn-core-supply = <&pm8994_l19>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ntn_default>;
+ qcom,ntn-rst-delay-msec = <100>;
+ qcom,ntn-rc-num = <1>;
+ };