diff options
| author | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2016-08-10 14:19:33 -0700 |
|---|---|---|
| committer | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2016-10-25 15:31:29 -0700 |
| commit | d329766ce2c336e4f83b104c826f729236c53340 (patch) | |
| tree | 901433c8adc0032acaaf21926f85b16abb76fca0 /Documentation | |
| parent | 448d10ae994b80d541960c34e6d2d8b3d060ea5b (diff) | |
clk: msm: osm: add support for configuring ACD block
ACD is a hardware block which mitigates the impact of VDD
supply droops on processor performance and energy efficiency.
It has direct interfaces with OSM to trigger recalibration
during DCVS operations. Add support to configure ACD during
boot to allow the CPU clock source to be switched to ACD
before DCVS transactions handled by OSM begin.
CRs-Fixed: 1053383
Change-Id: I712074a913b5603708542b71f5947e5ad43c8a5d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/qcom,osm.txt | 47 |
1 files changed, 44 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt index c4d651e36d02..782fb6c4124d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt @@ -18,13 +18,15 @@ Properties: Definition: Addresses and sizes for the memory of the OSM controller, cluster PLL management, and APCS common register regions. Optionally, the address of the efuse registers used to - determine the pwrcl or perfcl speed-bins. + determine the pwrcl or perfcl speed-bins and/or the ACD + register space to initialize prior to enabling OSM. + - reg-names Usage: required Value type: <stringlist> Definition: Address names. Must be "osm", "pwrcl_pll", "perfcl_pll", - "apcs_common" and "debug". Optionally, "pwrcl_efuse" or - "perfcl_efuse". + "apcs_common", and "debug". Optionally, "pwrcl_efuse", + "perfcl_efuse", "pwrcl_acd", or "perfcl_acd". Must be specified in the same order as the corresponding addresses are specified in the reg property. @@ -216,6 +218,45 @@ Properties: override values to write to the OSM controller for each of the two clusters. Each tuple must contain three elements. +- qcom,acdtd-val + Usage: required if pwrcl_acd or perfcl_acd registers are specified + Value type: <prop-encoded-array> + Definition: Array which defines the values to program to the ACD + Tunable-Length Delay register for the power and performance + clusters. + +- qcom,acdcr-val + Usage: required if pwrcl_acd or perfcl_acd registers are specified + Value type: <prop-encoded-array> + Definition: Array which defines the values for the ACD control register + for the power and performance clusters. + +- qcom,acdsscr-val + Usage: required if pwrcl_acd or perfcl_acd registers are specified + Value type: <prop-encoded-array> + Definition: Array which defines the values for the ACD Soft Start Control + register for the power and performance clusters. + +- qcom,acdextint0-val + Usage: required if pwrcl_acd or perfcl_acd registers are specified + Value type: <prop-encoded-array> + Definition: Array which defines the initial values for the ACD + external interface configuration register for the power + and performance clusters. + +- qcom,acdextint1-val + Usage: required if pwrcl_acd or perfcl_acd registers are specified + Value type: <prop-encoded-array> + Definition: Array which defines the final values for the ACD + external interface configuration register for the power + and performance clusters. + +- qcom,acdautoxfer-val + Usage: required if pwrcl_acd or perfcl_acd registers are specified + Value type: <prop-encoded-array> + Definition: Array which defines the values for the ACD auto transfer + control register for the power and performance clusters. + - qcom,pwrcl-apcs-mem-acc-cfg Usage: required if qcom,osm-no-tz is specified Value type: <prop-encoded-array> |