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authorSuman Tatiraju <sumant@codeaurora.org>2016-01-26 14:23:29 -0800
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 21:20:00 -0700
commitdc29065dc2ed55594b85755268ec34215e813341 (patch)
treef41e8fb6cc937b8e71b6b93aeb2db57b56c8f956 /Documentation
parent51b6ab4d7bc3737ebd488ccb30c6e7365aa551c7 (diff)
msm: kgsl: Read speed bin information from device tree
Speed bin information is sometimes written to efuses to specify a GPU frequency plan available on a platform. The current code only supports reading the efuses for msm8996v3. Hence specify it in the platform device tree node to support multiple platforms. CRs-Fixed: 967494 Change-Id: I5db4d5a35e2700250517ea6cac3d4d736936ce9f Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/gpu/adreno.txt6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpu/adreno.txt b/Documentation/devicetree/bindings/gpu/adreno.txt
index f6d45c2f431d..3a1af5030738 100644
--- a/Documentation/devicetree/bindings/gpu/adreno.txt
+++ b/Documentation/devicetree/bindings/gpu/adreno.txt
@@ -111,6 +111,12 @@ Optional Properties:
- qcom,gpu-quirk-two-pass-use-wfi:
Signal the GPU to set Set TWOPASSUSEWFI bit in
A5XX_PC_DBG_ECO_CNTL (5XX only)
+- qcom,gpu-speed-bin: GPU speed bin information in the format
+ <offset mask shift>
+ offset - offset of the efuse register from the base.
+ mask - mask for the relevant bits in the efuse register.
+ shift - number of bits to right shift to get the speed bin
+ value.
- qcom,l2pc-cpu-mask:
Disables L2PC on masked CPUs when any of Graphics