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| author | Stephen Boyd <sboyd@codeaurora.org> | 2015-10-02 11:29:54 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-10-02 11:29:54 -0700 |
| commit | c0d625cbb541ae68ca3c97fb62f5f6093d3382fa (patch) | |
| tree | c67ca474f4fd998829591b50b6f47e58d5b7c8df /arch/alpha/lib | |
| parent | 3b4261dcf65993f95de80a0d63c5299aab922bd8 (diff) | |
| parent | 9f30a04d768f64280dc0c40b730746e82f298d88 (diff) | |
Merge branch 'clk-fixes' into clk-next
* clk-fixes: (3 commits)
clk: ti: dflt: fix enable_reg validity check
clk: ti: fix dual-registration of uart4_ick
clk: ti: clk-7xx: Remove hardwired ABE clock configuration
Diffstat (limited to 'arch/alpha/lib')
| -rw-r--r-- | arch/alpha/lib/udelay.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/alpha/lib/udelay.c b/arch/alpha/lib/udelay.c index 69d52aa37bae..f2d81ff38aa6 100644 --- a/arch/alpha/lib/udelay.c +++ b/arch/alpha/lib/udelay.c @@ -30,6 +30,7 @@ __delay(int loops) " bgt %0,1b" : "=&r" (tmp), "=r" (loops) : "1"(loops)); } +EXPORT_SYMBOL(__delay); #ifdef CONFIG_SMP #define LPJ cpu_data[smp_processor_id()].loops_per_jiffy |