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authorVivek Gautam <gautam.vivek@samsung.com>2014-05-16 06:37:03 +0900
committerKukjin Kim <kgene.kim@samsung.com>2014-05-19 23:13:53 +0900
commit3cb7d1cdbec054ac08e7166578d8a53cbc429c33 (patch)
treeb6bd5d31d56cf2033b96fc84a58db3ab857c0dc8 /arch/arm/boot
parent6ac189fc85ea627fe92d7e9aed7426d08f43b240 (diff)
ARM: dts: Enable support for USB 3.0 PHY controller for exynos5420
Add device tree nodes for USB 3.0 PHY present alongwith USB 3.0 controller Exynos 5420 SoC. This phy driver is based on generic phy framework. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 384f7a2f91ed..31d99b0a2022 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -47,6 +47,8 @@
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
+ usbdrdphy0 = &usbdrd_phy0;
+ usbdrdphy1 = &usbdrd_phy1;
};
cpus {
@@ -755,4 +757,22 @@
clock-names = "secss";
samsung,power-domain = <&g2d_pd>;
};
+
+ usbdrd_phy0: phy@12100000 {
+ compatible = "samsung,exynos5420-usbdrd-phy";
+ reg = <0x12100000 0x100>;
+ clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ };
+
+ usbdrd_phy1: phy@12500000 {
+ compatible = "samsung,exynos5420-usbdrd-phy";
+ reg = <0x12500000 0x100>;
+ clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ };
};