diff options
| author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2015-01-22 16:54:50 +0100 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2015-01-26 13:43:33 +0100 |
| commit | bf02280e435cb620b255bb03738ac334cb7233dd (patch) | |
| tree | 617b9409e381c45e07fec9942e98f17b37b25d19 /arch/arm/mach-at91/pm.c | |
| parent | 42dfd1e10c9a50146656c32da667f1a7ff280325 (diff) | |
ARM: at91: fix PM initialization for newer SoCs
Newer SoCs: at91sam9x5, at91sam9n12, sama5d3 and sama5d4 embed a DDR controller
and have a different PMC status register layout than the at91sam9g45. Create
another at91_sam9x5_pm_init() function to match this compatibility.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm.c')
| -rw-r--r-- | arch/arm/mach-at91/pm.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 81f2f12d3cc1..87c1fd8aa1b6 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -306,3 +306,10 @@ void __init at91_sam9g45_pm_init(void) at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; return at91_pm_init(); } + +void __init at91_sam9x5_pm_init(void) +{ + at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; + at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; + return at91_pm_init(); +} |