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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-10-06 17:12:25 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-10-13 17:11:28 +0100
commitb1b3f49ce4606452279b58b17f2bbe2ba00304b7 (patch)
treec9cfdc72dd580a9c3ace71846af45b4f65268f46 /arch/arm/mach-tegra/Kconfig
parent4f1cd91497774488ed16119ec3f54b3daf1561de (diff)
ARM: config: sort select statements alphanumerically
As suggested by Andrew Morton: This is a pet peeve of mine. Any time there's a long list of items (header file inclusions, kconfig entries, array initalisers, etc) and someone wants to add a new item, they *always* go and stick it at the end of the list. Guys, don't do this. Either put the new item into a randomly-chosen position or, probably better, alphanumerically sort the list. lets sort all our select statements alphanumerically. This commit was created by the following perl: while (<>) { while (/\\\s*$/) { $_ .= <>; } undef %selects if /^\s*config\s+/; if (/^\s+select\s+(\w+).*/) { if (defined($selects{$1})) { if ($selects{$1} eq $_) { print STDERR "Warning: removing duplicated $1 entry\n"; } else { print STDERR "Error: $1 differently selected\n". "\tOld: $selects{$1}\n". "\tNew: $_\n"; exit 1; } } $selects{$1} = $_; next; } if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or /^endif/ or /^endchoice/)) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } undef %selects; } print; } if (%selects) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } } It found two duplicates: Warning: removing duplicated S5P_SETUP_MIPIPHY entry Warning: removing duplicated HARDIRQS_SW_RESEND entry and they are identical duplicates, hence the shrinkage in the diffstat of two lines. We have four testers reporting success of this change (Tony, Stephen, Linus and Sekhar.) Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-tegra/Kconfig')
-rw-r--r--arch/arm/mach-tegra/Kconfig32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 11680c532b38..9ff6f6ea3617 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -4,42 +4,42 @@ comment "NVIDIA Tegra options"
config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
- select CPU_V7
- select ARM_GIC
select ARCH_REQUIRE_GPIOLIB
- select PINCTRL
- select PINCTRL_TEGRA20
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB
- select USB_ULPI_VIEWPORT if USB_SUPPORT
select ARM_ERRATA_720789
select ARM_ERRATA_742230
select ARM_ERRATA_751472
select ARM_ERRATA_754327
select ARM_ERRATA_764369 if SMP
+ select ARM_GIC
+ select CPU_FREQ_TABLE if CPU_FREQ
+ select CPU_V7
+ select PINCTRL
+ select PINCTRL_TEGRA20
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
- select CPU_FREQ_TABLE if CPU_FREQ
+ select USB_ARCH_HAS_EHCI if USB_SUPPORT
+ select USB_ULPI if USB
+ select USB_ULPI_VIEWPORT if USB_SUPPORT
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
- select CPU_V7
- select ARM_GIC
select ARCH_REQUIRE_GPIOLIB
- select PINCTRL
- select PINCTRL_TEGRA30
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB
- select USB_ULPI_VIEWPORT if USB_SUPPORT
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
- select PL310_ERRATA_769419 if CACHE_L2X0
+ select ARM_GIC
select CPU_FREQ_TABLE if CPU_FREQ
+ select CPU_V7
+ select PINCTRL
+ select PINCTRL_TEGRA30
+ select PL310_ERRATA_769419 if CACHE_L2X0
+ select USB_ARCH_HAS_EHCI if USB_SUPPORT
+ select USB_ULPI if USB
+ select USB_ULPI_VIEWPORT if USB_SUPPORT
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller