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authorKukjin Kim <kgene.kim@samsung.com>2011-10-04 19:41:43 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 19:48:42 +0900
commit52e329ebb05983153bbde7351c94449018651290 (patch)
tree13b266d0cf3210eb1fa1057176fb19249099eb95 /arch/arm/plat-s3c24xx
parentc0468b0244464a9d85e527fd0bfee91caed697a7 (diff)
ARM: SAMSUNG: Consolidate plat/pll.h
Removed - arch/arm/plat-s3c24xx/include/plat/pll.h - arch/arm/mach-s3c64xx/include/mach/pll.h - arch/arm/plat-s5p/include/plat/pll.h - arch/arm/plat-samsung/include/plat/pll6553x.h And created - arch/arm/plat-samsung/include/plat/pll.h Cc: Ben Dooks <ben-linux@fluff.org> [kgene.kim@samsung.com: changed title] [kgene.kim@samsung.com: fixed conflicts in plat-s5p/include/pll.h] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pll.h62
1 files changed, 0 insertions, 62 deletions
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
deleted file mode 100644
index 005729a1077a..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/pll.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
- *
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C24xx - common pll registers and code
- */
-
-#define S3C24XX_PLLCON_MDIVSHIFT 12
-#define S3C24XX_PLLCON_PDIVSHIFT 4
-#define S3C24XX_PLLCON_SDIVSHIFT 0
-#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
-#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
-#define S3C24XX_PLLCON_SDIVMASK 3
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
-{
- unsigned int mdiv, pdiv, sdiv;
- uint64_t fvco;
-
- mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
- pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
- sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
-
- mdiv &= S3C24XX_PLLCON_MDIVMASK;
- pdiv &= S3C24XX_PLLCON_PDIVMASK;
- sdiv &= S3C24XX_PLLCON_SDIVMASK;
-
- fvco = (uint64_t)baseclk * (mdiv + 8);
- do_div(fvco, (pdiv + 2) << sdiv);
-
- return (unsigned int)fvco;
-}
-
-#define S3C2416_PLL_M_SHIFT (14)
-#define S3C2416_PLL_P_SHIFT (5)
-#define S3C2416_PLL_S_MASK (7)
-#define S3C2416_PLL_M_MASK ((1 << 10) - 1)
-#define S3C2416_PLL_P_MASK (63)
-
-static inline unsigned int
-s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
-{
- unsigned int m, p, s;
- uint64_t fvco;
-
- m = pllval >> S3C2416_PLL_M_SHIFT;
- p = pllval >> S3C2416_PLL_P_SHIFT;
-
- s = pllval & S3C2416_PLL_S_MASK;
- m &= S3C2416_PLL_M_MASK;
- p &= S3C2416_PLL_P_MASK;
-
- fvco = (uint64_t)baseclk * m;
- do_div(fvco, (p << s));
-
- return (unsigned int)fvco;
-}