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authorWill Deacon <will.deacon@arm.com>2013-06-05 12:40:34 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2013-06-07 18:00:11 +0100
commit737c16dffc458e58ee7840556d43b874cb8e16a0 (patch)
tree298c257517f97ad21236588c189c3e1e5bd38aa7 /arch/arm64
parent4ecf7ccb1973fd826456b6ab1e6dfafe9023c753 (diff)
arm64: mm: don't bother invalidating the icache in switch_mm
We don't support software broadcast of cache maintenance operations, so this flush is not required (__sync_icache_dcache will always affect all CPUs). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/include/asm/mmu_context.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index e2bc385adb6b..a9eee33dfa62 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -151,12 +151,6 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
{
unsigned int cpu = smp_processor_id();
-#ifdef CONFIG_SMP
- /* check for possible thread migration */
- if (!cpumask_empty(mm_cpumask(next)) &&
- !cpumask_test_cpu(cpu, mm_cpumask(next)))
- __flush_icache_all();
-#endif
if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
check_and_switch_context(next, tsk);
}