diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2006-03-16 14:10:20 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-03-16 14:10:20 +0000 |
| commit | 9e7714d08061a77d3d2ec9a6ef6fd571a534fc7f (patch) | |
| tree | e279d51b007c5f3d6b4cf157c1fada7ea7fe39da /arch/arm | |
| parent | 243f196d572822214bb86522f28b30e096d67414 (diff) | |
[ARM] 3367/1: CLCD mode no longer supported on the RealView boards
Patch from Catalin Marinas
Chosing of the CLCD RGB mode is no longer possible via the SYS_CLCD
register on the RealView boards. Instead, this configuration is done in the
CLCD primecell control register directly.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-realview/core.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 4303d988c4bf..d13270c5d7cd 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -202,11 +202,6 @@ struct clk realview_clcd_clk = { /* * CLCD support. */ -#define SYS_CLCD_MODE_MASK (3 << 0) -#define SYS_CLCD_MODE_888 (0 << 0) -#define SYS_CLCD_MODE_5551 (1 << 0) -#define SYS_CLCD_MODE_565_RLSB (2 << 0) -#define SYS_CLCD_MODE_565_BLSB (3 << 0) #define SYS_CLCD_NLCDIOON (1 << 2) #define SYS_CLCD_VDDPOSSWITCH (1 << 3) #define SYS_CLCD_PWR3V5SWITCH (1 << 4) @@ -360,29 +355,10 @@ static void realview_clcd_enable(struct clcd_fb *fb) void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; u32 val; - val = readl(sys_clcd); - val &= ~SYS_CLCD_MODE_MASK; - - switch (fb->fb.var.green.length) { - case 5: - val |= SYS_CLCD_MODE_5551; - break; - case 6: - val |= SYS_CLCD_MODE_565_RLSB; - break; - case 8: - val |= SYS_CLCD_MODE_888; - break; - } - - /* - * Set the MUX - */ - writel(val, sys_clcd); - /* - * And now enable the PSUs + * Enable the PSUs */ + val = readl(sys_clcd); val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; writel(val, sys_clcd); } |