diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-02-10 21:40:19 +0530 |
|---|---|---|
| committer | Benoit Cousson <benoit.cousson@linaro.org> | 2013-04-09 00:21:15 +0200 |
| commit | b45ccc4e4923ad4c9d1b541f52b2b33facd3b0c5 (patch) | |
| tree | 6d7eade32869b3793097618bedf6c85d3e3cad74 /arch/arm | |
| parent | 03178c66d289b8188483dc0d823e75dbab083ccc (diff) | |
ARM: dts: OMAP5: Align the local timer dt node as per the current binding code
It has been decided to not duplicate banked modules dt nodes and that is
how the current arch timer dt extraction code is.
Update the OMAP5 DT file accordingly.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 19 |
1 files changed, 7 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b760c116e7f7..aefecf7ca574 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -33,24 +33,19 @@ cpus { cpu@0 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - /* 14th PPI IRQ, active low level-sensitive */ - interrupts = <1 14 0x308>; - clock-frequency = <6144000>; - }; }; cpu@1 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - /* 14th PPI IRQ, active low level-sensitive */ - interrupts = <1 14 0x308>; - clock-frequency = <6144000>; - }; }; }; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. |