diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-07-27 19:26:58 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-07-27 19:26:58 -0700 |
| commit | ea40856447043a29977f9078ede07cf2cf29f0ed (patch) | |
| tree | bc3fd8c80c48f2ecd9e0fd0122cddf45370c15d7 /arch/arm | |
| parent | 69493c178dcebba4cfe0d92c8bd05b68e86f4bab (diff) | |
| parent | b20d7ec122de21f460fc72e7f7e76122b846a84c (diff) | |
Merge "clk: msm: clock: Remove support for the USB cfg_ahb2phy clock from HLOS"
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 60117b4fc302..f02abd2173ef 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -1727,11 +1727,10 @@ <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, <&clock_gcc clk_gcc_usb30_sleep_clk>, - <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_cxo_dwc3_clk>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; + "utmi_clk", "sleep_clk", "xo"; dwc3@a800000 { compatible = "snps,dwc3"; @@ -1799,11 +1798,9 @@ clocks = <&clock_gcc clk_ln_bb_clk1>, <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>, - <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_qusb2phy_prim_reset>; - clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", - "phy_reset"; + clock-names = "ref_clk_src", "ref_clk", "phy_reset"; }; ssphy: ssphy@c010000 { @@ -1951,13 +1948,12 @@ clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, - <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_usb3_phy_reset>, <&clock_gcc clk_gcc_usb3phy_phy_reset>, <&clock_gcc clk_ln_bb_clk1>, <&clock_gcc clk_gcc_usb3_clkref_clk>; - clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset", + clock-names = "aux_clk", "pipe_clk", "phy_reset", "phy_phy_reset", "ref_clk_src", "ref_clk"; }; |