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authorSonic Zhang <sonic.zhang@analog.com>2012-12-14 11:19:24 +0800
committerBob Liu <lliubbo@gmail.com>2012-12-14 11:20:22 +0800
commit86794b43569c9b8936dff2e8eed503393379af6e (patch)
treea1e22a88f584c300792167de4b59bae7ec37d9a3 /arch/blackfin/include
parent1439d030b9032261f1111a2dd16b9a8ca11112ef (diff)
blackfin: SEC: clean up SEC interrupt initialization
Append the SEC IRQ after the IVG6, which is consistent to BF5xx SIC. Exclude SIC irqchip fucntions from SEC code. Call handle_fasteoi_irq in SEC error and fault handler. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r--arch/blackfin/include/mach-common/irq.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
index cab14e911dc2..af9fc8171ebc 100644
--- a/arch/blackfin/include/mach-common/irq.h
+++ b/arch/blackfin/include/mach-common/irq.h
@@ -40,8 +40,6 @@
#define IRQ_HWERR 5 /* Hardware Error */
#define IRQ_CORETMR 6 /* Core timer */
-#define BFIN_IRQ(x) ((x) + 7)
-
#define IVG7 7
#define IVG8 8
#define IVG9 9
@@ -52,6 +50,9 @@
#define IVG14 14
#define IVG15 15
+#define BFIN_IRQ(x) ((x) + IVG7)
+#define BFIN_SYSIRQ(x) ((x) - IVG7)
+
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#endif