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authorAndi Kleen <andi@basil.nowhere.org>2006-11-21 10:22:09 +0100
committerAndi Kleen <andi@basil.nowhere.org>2006-11-21 10:22:09 +0100
commit1b7f6a626f0ff511c3840678466cbfe1d62c0b29 (patch)
tree415e8c838c0067bff384afb8a2c91e5f7c6d11d3 /arch/mips/mm/c-sb1.c
parentb3edc9cec07ade41aaf1804f7c9e876afa90c862 (diff)
parent3f5a6ca31c334011fd929501a078424c0d3f71be (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/mips/mm/c-sb1.c')
-rw-r--r--arch/mips/mm/c-sb1.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index 5537558f19f7..d0ddb4a768a5 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -49,6 +49,15 @@ static unsigned short dcache_sets;
static unsigned int icache_range_cutoff;
static unsigned int dcache_range_cutoff;
+static inline void sb1_on_each_cpu(void (*func) (void *info), void *info,
+ int retry, int wait)
+{
+ preempt_disable();
+ smp_call_function(func, info, retry, wait);
+ func(info);
+ preempt_enable();
+}
+
/*
* The dcache is fully coherent to the system, with one
* big caveat: the instruction stream. In other words,
@@ -226,7 +235,7 @@ static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
args.vma = vma;
args.addr = addr;
args.pfn = pfn;
- on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
+ sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
}
#else
void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
@@ -249,7 +258,7 @@ void sb1___flush_cache_all_ipi(void *ignored)
static void sb1___flush_cache_all(void)
{
- on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
+ sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
}
#else
void sb1___flush_cache_all(void)
@@ -299,7 +308,7 @@ void sb1_flush_icache_range(unsigned long start, unsigned long end)
args.start = start;
args.end = end;
- on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
+ sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
}
#else
void sb1_flush_icache_range(unsigned long start, unsigned long end)
@@ -326,7 +335,7 @@ static void sb1_flush_cache_sigtramp_ipi(void *info)
static void sb1_flush_cache_sigtramp(unsigned long addr)
{
- on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
+ sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
}
#else
void sb1_flush_cache_sigtramp(unsigned long addr)
@@ -444,7 +453,6 @@ static __init void probe_cache_sizes(void)
void sb1_cache_init(void)
{
extern char except_vec2_sb1;
- extern char handle_vec2_sb1;
/* Special cache error handler for SB1 */
set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
@@ -497,5 +505,5 @@ void sb1_cache_init(void)
:
: "memory");
- flush_cache_all();
+ local_sb1___flush_cache_all();
}