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authorSteven J. Hill <Steven.Hill@imgtec.com>2014-11-13 09:52:02 -0600
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 22:47:31 +0100
commite2965cd0003f222bd49f67907c2bc6ed691c6d20 (patch)
tree178e452f7078122ed59c78c19d4bb2c78036505c /arch/mips/mm/uasm.c
parent77a5c59332aa75e66f0d95f9eeb69baf3c68970d (diff)
MIPS: Add MFHC0 and MTHC0 instructions to uasm.
New instructions for Extended Physical Addressing (XPA) functionality. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8453/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/uasm.c')
-rw-r--r--arch/mips/mm/uasm.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index a01b0d6cedd2..4adf30284813 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -51,12 +51,12 @@ enum opcode {
insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
- insn_lwx, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul,
- insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
- insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra,
- insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
- insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
- insn_xor, insn_xori, insn_yield,
+ insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,
+ insn_mthc0, insn_mul, insn_or, insn_ori, insn_pref, insn_rfe,
+ insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_slt,
+ insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu,
+ insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi,
+ insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield,
};
struct insn {
@@ -284,9 +284,11 @@ I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u1u2u3(_mfc0)
+I_u1u2u3(_mfhc0)
I_u1(_mfhi)
I_u1(_mflo)
I_u1u2u3(_mtc0)
+I_u1u2u3(_mthc0)
I_u3u1u2(_mul)
I_u2u1u3(_ori)
I_u3u1u2(_or)