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| author | Michael Bestas <mkbestas@lineageos.org> | 2020-10-23 18:21:25 +0300 |
|---|---|---|
| committer | Michael Bestas <mkbestas@lineageos.org> | 2020-10-23 18:21:25 +0300 |
| commit | 794b42a9a5fd60bd14413abedafdd2a9b07b1308 (patch) | |
| tree | 2c00d2a954de42f9dc54b3a7894c1ad99a2e8a8b /arch/mips | |
| parent | 24b3bdcf71522f4d711958b01e8a8f234fe2450d (diff) | |
| parent | 7a9986e91f90994623e4c5de1effce14729dba96 (diff) | |
Merge branch 'android-4.4-p' of https://android.googlesource.com/kernel/common into lineage-17.1-caf-msm8998
This brings LA.UM.8.4.r1-06000-8x98.0 up to date with
https://android.googlesource.com/kernel/common/ android-4.4-p at commit:
7a9986e91f909 UPSTREAM: binder: fix UAF when releasing todo list
Conflicts:
fs/eventpoll.c
Change-Id: I77260d03cb539d7e7eefcea360aee2d59bb9e0cb
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/Kconfig | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/cpu-type.h | 1 | ||||
| -rw-r--r-- | arch/mips/sni/a20r.c | 9 |
3 files changed, 9 insertions, 2 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 29b4bde7899c..17aa92272f9b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -870,6 +870,7 @@ config SNI_RM select I8253 select I8259 select ISA + select MIPS_L1_CACHE_SHIFT_6 select SWAP_IO_SPACE if CPU_BIG_ENDIAN select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index abee2bfd10dc..cea0bbb71590 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -46,6 +46,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) case CPU_34K: case CPU_1004K: case CPU_74K: + case CPU_1074K: case CPU_M14KC: case CPU_M14KEC: case CPU_INTERAPTIV: diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c index f9407e170476..c6af7047eb0d 100644 --- a/arch/mips/sni/a20r.c +++ b/arch/mips/sni/a20r.c @@ -143,7 +143,10 @@ static struct platform_device sc26xx_pdev = { }, }; -static u32 a20r_ack_hwint(void) +/* + * Trigger chipset to update CPU's CAUSE IP field + */ +static u32 a20r_update_cause_ip(void) { u32 status = read_c0_status(); @@ -205,12 +208,14 @@ static void a20r_hwint(void) int irq; clear_c0_status(IE_IRQ0); - status = a20r_ack_hwint(); + status = a20r_update_cause_ip(); cause = read_c0_cause(); irq = ffs(((cause & status) >> 8) & 0xf8); if (likely(irq > 0)) do_IRQ(SNI_A20R_IRQ_BASE + irq - 1); + + a20r_update_cause_ip(); set_c0_status(IE_IRQ0); } |