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authorPaul Mundt <lethal@linux-sh.org>2010-02-08 11:34:03 +0900
committerPaul Mundt <lethal@linux-sh.org>2010-02-08 11:34:03 +0900
commit2e18e047981ae04be9bd0d9760057f7c1a7b3785 (patch)
tree999941abf466ce4d6915273e2e7a42bf0a107385 /arch/sh
parentb06ede84dd1473dec7c6af03a41c8d04d2fee437 (diff)
parentcfefe99795251d76d92e8457f4152f532a961ec5 (diff)
Merge branch 'sh/dmaengine'
Conflicts: arch/sh/drivers/dma/dma-sh.c
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/drivers/dma/dma-sh.c5
-rw-r--r--arch/sh/include/asm/dma-sh.h43
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h20
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h108
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h35
5 files changed, 155 insertions, 56 deletions
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 565cc1a4cbba..827208781ed5 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -52,11 +52,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
*
* iterations to complete the transfer.
*/
+static unsigned int ts_shift[] = TS_SHIFT;
static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
{
u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
+ int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
+ ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
- return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
+ return ts_shift[cnt];
}
/*
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index 47de10976991..e934a2e66651 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -64,8 +64,10 @@ static int dmte_irq_map[] __maybe_unused = {
#define ACK_L 0x00010000
#define DM_INC 0x00004000
#define DM_DEC 0x00008000
+#define DM_FIX 0x0000c000
#define SM_INC 0x00001000
#define SM_DEC 0x00002000
+#define SM_FIX 0x00003000
#define RS_IN 0x00000200
#define RS_OUT 0x00000300
#define TS_BLK 0x00000040
@@ -83,7 +85,7 @@ static int dmte_irq_map[] __maybe_unused = {
* Define the default configuration for dual address memory-memory transfer.
* The 0x400 value represents auto-request, external->external.
*/
-#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
+#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
/* DMA base address */
static u32 dma_base_addr[] __maybe_unused = {
@@ -123,10 +125,47 @@ static u32 dma_base_addr[] __maybe_unused = {
*/
#define SHDMA_MIX_IRQ (1 << 1)
#define SHDMA_DMAOR1 (1 << 2)
-#define SHDMA_DMAE1 (1 << 3)
+#define SHDMA_DMAE1 (1 << 3)
+
+enum sh_dmae_slave_chan_id {
+ SHDMA_SLAVE_SCIF0_TX,
+ SHDMA_SLAVE_SCIF0_RX,
+ SHDMA_SLAVE_SCIF1_TX,
+ SHDMA_SLAVE_SCIF1_RX,
+ SHDMA_SLAVE_SCIF2_TX,
+ SHDMA_SLAVE_SCIF2_RX,
+ SHDMA_SLAVE_SCIF3_TX,
+ SHDMA_SLAVE_SCIF3_RX,
+ SHDMA_SLAVE_SCIF4_TX,
+ SHDMA_SLAVE_SCIF4_RX,
+ SHDMA_SLAVE_SCIF5_TX,
+ SHDMA_SLAVE_SCIF5_RX,
+ SHDMA_SLAVE_SIUA_TX,
+ SHDMA_SLAVE_SIUA_RX,
+ SHDMA_SLAVE_SIUB_TX,
+ SHDMA_SLAVE_SIUB_RX,
+ SHDMA_SLAVE_NUMBER, /* Must stay last */
+};
+
+struct sh_dmae_slave_config {
+ enum sh_dmae_slave_chan_id slave_id;
+ dma_addr_t addr;
+ u32 chcr;
+ char mid_rid;
+};
struct sh_dmae_pdata {
unsigned int mode;
+ struct sh_dmae_slave_config *config;
+ int config_num;
+};
+
+struct device;
+
+struct sh_dmae_slave {
+ enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
+ struct device *dma_dev; /* Set by the platform */
+ struct sh_dmae_slave_config *config; /* Set by the driver */
};
#endif /* __DMA_SH_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 0ea15f3f2363..207811a7a650 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -20,8 +20,10 @@
#define TS_32 0x00000010
#define TS_128 0x00000018
-#define CHCR_TS_MASK 0x18
-#define CHCR_TS_SHIFT 3
+#define CHCR_TS_LOW_MASK 0x18
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
#define DMAOR_INIT DMAOR_DME
@@ -36,11 +38,13 @@ enum {
XMIT_SZ_128BIT,
};
-static unsigned int ts_shift[] __maybe_unused = {
- [XMIT_SZ_8BIT] = 0,
- [XMIT_SZ_16BIT] = 1,
- [XMIT_SZ_32BIT] = 2,
- [XMIT_SZ_128BIT] = 4,
-};
+#define TS_SHIFT { \
+ [XMIT_SZ_8BIT] = 0, \
+ [XMIT_SZ_16BIT] = 1, \
+ [XMIT_SZ_32BIT] = 2, \
+ [XMIT_SZ_128BIT] = 4, \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index c4ed660c14cf..e734ea47d8a0 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -2,22 +2,38 @@
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
- defined(CONFIG_CPU_SUBTYPE_SH7722) || \
defined(CONFIG_CPU_SUBTYPE_SH7730)
#define DMTE0_IRQ 48
#define DMTE4_IRQ 76
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
-#define SH_DMARS_BASE 0xFE009000
+#define SH_DMARS_BASE0 0xFE009000
+#define CHCR_TS_LOW_MASK 0x00000018
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
+#define DMTE0_IRQ 48
+#define DMTE4_IRQ 76
+#define DMAE0_IRQ 78 /* DMA Error IRQ*/
+#define SH_DMAC_BASE0 0xFE008020
+#define SH_DMARS_BASE0 0xFE009000
+#define CHCR_TS_LOW_MASK 0x00000018
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0x00300000
+#define CHCR_TS_HIGH_SHIFT 20
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7764)
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
#define DMAE0_IRQ 38
#define SH_DMAC_BASE0 0xFF608020
-#define SH_DMARS_BASE 0xFF609000
-#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
- defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define SH_DMARS_BASE0 0xFF609000
+#define CHCR_TS_LOW_MASK 0x00000018
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
#define DMTE0_IRQ 48 /* DMAC0A*/
#define DMTE4_IRQ 76 /* DMAC0B */
#define DMTE6_IRQ 40
@@ -29,7 +45,29 @@
#define DMAE1_IRQ 74 /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMAC_BASE1 0xFDC08020
-#define SH_DMARS_BASE 0xFDC09000
+#define SH_DMARS_BASE0 0xFDC09000
+#define CHCR_TS_LOW_MASK 0x00000018
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define DMTE0_IRQ 48 /* DMAC0A*/
+#define DMTE4_IRQ 76 /* DMAC0B */
+#define DMTE6_IRQ 40
+#define DMTE8_IRQ 42 /* DMAC1A */
+#define DMTE9_IRQ 43
+#define DMTE10_IRQ 72 /* DMAC1B */
+#define DMTE11_IRQ 73
+#define DMAE0_IRQ 78 /* DMA Error IRQ*/
+#define DMAE1_IRQ 74 /* DMA Error IRQ*/
+#define SH_DMAC_BASE0 0xFE008020
+#define SH_DMAC_BASE1 0xFDC08020
+#define SH_DMARS_BASE0 0xFE009000
+#define SH_DMARS_BASE1 0xFDC09000
+#define CHCR_TS_LOW_MASK 0x00000018
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0x00600000
+#define CHCR_TS_HIGH_SHIFT 21
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
@@ -41,7 +79,11 @@
#define DMAE0_IRQ 38 /* DMA Error IRQ */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFC818020
-#define SH_DMARS_BASE 0xFC809000
+#define SH_DMARS_BASE0 0xFC809000
+#define CHCR_TS_LOW_MASK 0x00000018
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
#else /* SH7785 */
#define DMTE0_IRQ 33
#define DMTE4_IRQ 37
@@ -54,18 +96,17 @@
#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFCC08020
-#define SH_DMARS_BASE 0xFC809000
+#define SH_DMARS_BASE0 0xFC809000
+#define CHCR_TS_LOW_MASK 0x00000018
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
#endif
-#define REQ_HE 0x000000C0
-#define REQ_H 0x00000080
-#define REQ_LE 0x00000040
-#define TM_BURST 0x0000020
-#define TS_8 0x00000000
-#define TS_16 0x00000008
-#define TS_32 0x00000010
-#define TS_16BLK 0x00000018
-#define TS_32BLK 0x00100000
+#define REQ_HE 0x000000C0
+#define REQ_H 0x00000080
+#define REQ_LE 0x00000040
+#define TM_BURST 0x00000020
/*
* The SuperH DMAC supports a number of transmit sizes, we list them here,
@@ -74,22 +115,31 @@
* Defaults to a 64-bit transfer size.
*/
enum {
- XMIT_SZ_8BIT,
- XMIT_SZ_16BIT,
- XMIT_SZ_32BIT,
- XMIT_SZ_128BIT,
- XMIT_SZ_256BIT,
+ XMIT_SZ_8BIT = 0,
+ XMIT_SZ_16BIT = 1,
+ XMIT_SZ_32BIT = 2,
+ XMIT_SZ_64BIT = 7,
+ XMIT_SZ_128BIT = 3,
+ XMIT_SZ_256BIT = 4,
+ XMIT_SZ_128BIT_BLK = 0xb,
+ XMIT_SZ_256BIT_BLK = 0xc,
};
/*
* The DMA count is defined as the number of bytes to transfer.
*/
-static unsigned int ts_shift[] __maybe_unused = {
- [XMIT_SZ_8BIT] = 0,
- [XMIT_SZ_16BIT] = 1,
- [XMIT_SZ_32BIT] = 2,
- [XMIT_SZ_128BIT] = 4,
- [XMIT_SZ_256BIT] = 5,
-};
+#define TS_SHIFT { \
+ [XMIT_SZ_8BIT] = 0, \
+ [XMIT_SZ_16BIT] = 1, \
+ [XMIT_SZ_32BIT] = 2, \
+ [XMIT_SZ_64BIT] = 3, \
+ [XMIT_SZ_128BIT] = 4, \
+ [XMIT_SZ_256BIT] = 5, \
+ [XMIT_SZ_128BIT_BLK] = 4, \
+ [XMIT_SZ_256BIT_BLK] = 5, \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
+ ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index bcb30246e85c..114a369705bc 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -6,8 +6,6 @@
#ifdef CONFIG_CPU_SH4A
#define DMAOR_INIT (DMAOR_DME)
-#define CHCR_TS_MASK 0x18
-#define CHCR_TS_SHIFT 3
#include <cpu/dma-sh4a.h>
#else /* CONFIG_CPU_SH4A */
@@ -29,8 +27,10 @@
#define TS_32 0x00000030
#define TS_64 0x00000000
-#define CHCR_TS_MASK 0x70
-#define CHCR_TS_SHIFT 4
+#define CHCR_TS_LOW_MASK 0x70
+#define CHCR_TS_LOW_SHIFT 4
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
#define DMAOR_COD 0x00000008
@@ -41,23 +41,26 @@
* Defaults to a 64-bit transfer size.
*/
enum {
- XMIT_SZ_64BIT,
- XMIT_SZ_8BIT,
- XMIT_SZ_16BIT,
- XMIT_SZ_32BIT,
- XMIT_SZ_256BIT,
+ XMIT_SZ_8BIT = 1,
+ XMIT_SZ_16BIT = 2,
+ XMIT_SZ_32BIT = 3,
+ XMIT_SZ_64BIT = 0,
+ XMIT_SZ_256BIT = 4,
};
/*
* The DMA count is defined as the number of bytes to transfer.
*/
-static unsigned int ts_shift[] __maybe_unused = {
- [XMIT_SZ_64BIT] = 3,
- [XMIT_SZ_8BIT] = 0,
- [XMIT_SZ_16BIT] = 1,
- [XMIT_SZ_32BIT] = 2,
- [XMIT_SZ_256BIT] = 5,
-};
+#define TS_SHIFT { \
+ [XMIT_SZ_8BIT] = 0, \
+ [XMIT_SZ_16BIT] = 1, \
+ [XMIT_SZ_32BIT] = 2, \
+ [XMIT_SZ_64BIT] = 3, \
+ [XMIT_SZ_256BIT] = 5, \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
+
#endif
#endif /* __ASM_CPU_SH4_DMA_H */