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| author | Max Filippov <jcmvbkbc@gmail.com> | 2013-03-04 03:40:42 +0400 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2013-05-09 01:07:09 -0700 |
| commit | d83ff0bb828854d9e7172ac5d8d007a7466934c9 (patch) | |
| tree | 188dfa08078c116698d4673a42a38b40e75a4ccb /arch/xtensa/kernel/head.S | |
| parent | 74f5bf029ee052e3d845672728e80b7240d14f09 (diff) | |
xtensa: fix ibreakenable register update
Only set the register when there is at least one ibreak register,
otherwise the build fails:
arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable'
for 'wsr' instruction
arch/xtensa/platforms/iss/setup.c:67: Error: invalid register
'ibreakenable' for 'wsr' instruction
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/kernel/head.S')
| -rw-r--r-- | arch/xtensa/kernel/head.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S index df88f98737f4..4566683abc8d 100644 --- a/arch/xtensa/kernel/head.S +++ b/arch/xtensa/kernel/head.S @@ -86,7 +86,9 @@ ENTRY(_startup) /* Clear debugging registers. */ #if XCHAL_HAVE_DEBUG +#if XCHAL_NUM_IBREAK > 0 wsr a0, ibreakenable +#endif wsr a0, icount movi a1, 15 wsr a0, icountlevel |